JPS631182A - Teletext receiving device - Google Patents

Abstract

PURPOSE:To stably store packet data even if the number of packets of the same program number and a page number is increased or decreased by dividing a packet memory circuit into the proper size of areas with the aid of a memory division control memory circuit and using them. CONSTITUTION:In a memory division control memory circuit 6 the head address of areas which are obtained by dividing the area of a packet memory circuit 3 by the plural kinds of sizes is previously written. An arithmetic control circuit 2 detects a program number, a page number and the number of packets from transmitted packet data. Next after searching a control memory circuit 4, whether or not the detected program number and page number have already existed is decided. And if the number of packets is different from a former value and inputted in the division area of the circuit 3 different from the former one, by searching the memory division control memory circuit 6, the memory use flag of the head address in the new applicable division area is set so as to rewrite the head address into the storage head address of the control memory circuit 4, so that the packet data can be written in the packet memory circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory management system for a teletext receiver having a large capacity packet memory circuit.

BACKGROUND OF THE INVENTION A conventional example of a teletext receiving device that can store all transmitted packet data page by page in a packet memory circuit, read out selected program data from the packet memory circuit, and immediately display it is described below. Shown in Figure 3. In the figure, 1 is a packet data input terminal, 2 is an arithmetic control circuit, 3 is a packet memory circuit, 4 is a memory management circuit, and 5 is a packet data input terminal.
is a packet data output terminal.

The packet data is read into the arithmetic control circuit 2 via the packet data input terminal 1, and the arithmetic control circuit 2 detects the program number, page number, and number of packets constituting the page from the packet data. . Furthermore, the memory management circuit 4 is searched to determine whether the detected program number and page number already exist. If the same program number and page number exist in the memory management circuit 4, the storage of packet data starts from the address in the packet memory circuit 3 indicated by the storage start address indicating the start address of the area for storing packet data. do.

In addition, if the same program number and page number do not exist in the memory management circuit 4, an unused area of the memory management circuit 4 is used to store information indicating the end of the storage area calculated from the program number, page number, storage start address, and number of packets. Write each terminal address. FIG. 4 is a diagram showing the contents and structure of the memory management circuit 4 in FIG. 3.

In this figure, in order to use the packet memory circuit 3 efficiently, for example, the data area of the first page of program number 10 and the data area of the third page of program number 11 are adjacent to each other.

In the case of screen display, when a program number and a page number are selected, the arithmetic control circuit 2 searches the management memory circuit 4, detects the storage start address of the matching page data, and retrieves the page data from the packet memory circuit 3. Although not shown here, the packet data is outputted to the image display unit via the packet data output terminal 6.

Problems to be Solved by the Invention In such conventional examples, the usage efficiency of the packet memory circuit is very good, but in programs where the screen content changes, such as news, it is difficult to use the packet data that makes up the screen. The number of packets will increase or decrease, and in particular, if the number of data increases, it will invade the page data area of the next stored program, resulting in data destruction.

On the other hand, if a large number of protected areas are provided between the storage end address of the page data of a certain program and the storage start address of the page data of the next received program, the usage efficiency of the packet memory circuit will deteriorate.

The present invention has been made in view of the above points, and it is possible to efficiently use a packet memory circuit, and to destroy packet data of other stored programs even if the number of packets of packet data constituting a program increases. To provide a teletext receiving device that stably stores packet data without any problems.

Means for Solving the Problems The teletext receiving apparatus of the present invention includes a packet memory circuit for storing packet data, a management memory circuit for managing packet data, and a packet memory circuit in multiple types of appropriately sized areas. It consists of a memory division management memory circuit and an arithmetic control circuit that record the usage status of the divided areas.

Function: The arithmetic control circuit detects the program number, page number, and number of packets from the packet data sent, and selects the first address to be used from the number of packets from the memory division management memory circuit in which the first address of the divided area is written in advance. , sets the memory use flag corresponding to this starting address, writes this starting address to the storage starting address of the management memory circuit,
Packet data is sequentially stored in a packet memory circuit.

Embodiment FIG. 1 is a circuit diagram of a teletext receiver according to an embodiment of the present invention, and since 1 to 5 have the same reference numerals as those in FIG. 3, the explanation thereof will be omitted. In FIG. 1, reference numeral 6 denotes a memory division management memory circuit, in which the area of the packet memory circuit 3 is divided into a plurality of sizes, the starting addresses of the divided areas are written in advance, and the memory use flag is set. It has been reset. FIG. 2 is a diagram showing the contents and configuration of the memory division management memory circuit 6 in FIG. 1. In this example, the area of the packet memory circuit 3 is divided into four sizes: 1 byte, 2 bytes, 4 bytes, and 8 bytes.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. First, the arithmetic control circuit 2 detects the program number, page number, and number of packets from the sent packet data. Next, the management memory circuit 4 is searched to determine whether the detected program number and page number already exist. If the number of packets already exists, it is determined whether the detected number of packets is the same as the previous value, that is, the number of packets in the management memory circuit 4. If the number of packets is the same, the packets and /) data are sequentially rewritten in the same area of the packet memory circuit 3. If the number of packets is different from the previous value, it is determined which divided area to enter, and if it is the same divided area as before, the same operation as above is performed. When entering a divided area different from the previous one, the memory division management memory circuit 6 is searched, the memory usage flag of the first address used by the corresponding program number and page number is reset, and the first address of the new corresponding divided area is reset. The memory use flag is set, this start address is rewritten to the storage start address of the management memory circuit 4, and the packet data is written into the packet memory circuit 3.

Furthermore, if the detected program number and page number do not exist in the management memory circuit 4, the program number and page number are written into the management memory circuit 4. Then, the memory division management circuit 6 determines which division area should be included based on the number of buckets.
and writes the corresponding storage start address to the management memory circuit 4, sets the memory use flag of the memory division management circuit, etc., and writes the packet data to the packet memory circuit 3.
I will remember it.

Effects of the Invention Since the packet memory circuit is divided into appropriately sized areas by the memory division management memory circuit,
Packet data can be stored stably even if the number of entries for the same program number and page number increases or decreases.
The effect is remarkable because memory is used efficiently.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a main part of a teletext receiving device according to an embodiment of the present invention, FIG. 2 is a diagram showing the contents and configuration of a memory management divided memory circuit in FIG. 1, and FIG. 3 is a conventional teletext reception device. FIG. 4 is a circuit diagram of the main part of the apparatus, and is a diagram showing the contents and configuration of the management memory circuit in FIG. 3. 1...Bucket data input terminal, 2...
・Arithmetic control circuit, 3...Packet memory circuit,
4... Management memory circuit, 6... Packet data output terminal, 6... Memory division management memory circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] a packet memory circuit for storing packet data of transmitted teletext; a management memory circuit used for managing the packet data; an arithmetic control circuit for performing arithmetic control on the packet memory circuit and the management memory circuit; A memory division management memory circuit is provided which divides the area of the memory circuit into multiple types of appropriate sizes and manages the usage status of the divided areas, and when storing a program, the packets of the packet data constituting the program are provided. A teletext receiving apparatus characterized in that an area specified by the memory division management memory circuit is selected from a number of sub-regions, and packet data is stored in the selected area.