JPS63115413A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To improve an output secondary distortion caused by the load capacity of an output part by securing difference between the forward charging time and the reverse charging direction of a capacitor that prescribes an oscillation frequency. CONSTITUTION:Transistors (TR) Q6 and Q7 are driven by the same voltage supplied from a constant voltage source 8. Then the current I1 flowing through the TR Q6 and the current I2 flowing through the TR Q7 have different levels as constant current in response to the ratio between resistances R3 and R4 owing to these two resistance having different resistance values. Thus the duty ratio of the oscillation output having 50% deviation due to the load capacity CL is corrected by 50% in terms of the center level of the oscillation amplitude. Thus, it is possible to reduce an output secondary distortion caused by the capacity CL.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation circuit, and particularly to improvement of output second-order distortion due to load capacitance of an output section.

[Conventional technology]

Figure 3 shows the generally known emitter-coupled multi-
FIG. 2 is a diagram showing a circuit configuration of an oscillation circuit using an oscillator. This circuit consists of a pair of amplifying transistors Q1. Q2, and transistors Q1. Q2 is an emitter follower buffer transistor Q3. Cross-connected via Q4. That is, the base of transistor Q is connected to the emitter of transistor Q3, and its collector is connected to the base of transistor Q4, while the base of transistor Q is connected to the emitter of transistor Q4, and its collector is connected to the base of transistor Q3. It is connected to the. As a result, transistor Q1. When one of Q2 is on, the other will be off.

1 is a power supply terminal, transistor Q1. The collector of Q2 is connected to the power supply voltage V through resistors R and R2 of equal value. Connected to 0. Dl.

D is a diode for clamping the voltage applied to the resistors R and R2, that is, the potential of the collectors of the transistors Q and Q2. The emitter of the transistor Q1.02 is grounded via a constant current source 2.3 for flowing an equal current (2). The constant current sources 2 and 3 are constituted by, for example, a well-known current mirror circuit consisting of two transistors having a common base and one collector and base connected. Transistor Q1. A timing capacitor C for determining the oscillation frequency is connected between the emitters of Q2, and is charged alternately in the forward direction and in the reverse direction by the current ■ flowing through the constant current source 2 or 3.

Transistor Q3. Oscillation outputs having mutually opposite phases are obtained from the emitter of transistor Q4, and in the illustrated circuit, the oscillation output obtained from the emitter of transistor Q3 is taken out to output terminal 4 via emitter follower transistor Q5. The collectors of transistors 03 to Q5 are at power supply voltage V. 0, and the emitters are grounded via constant current sources 5 to 7, respectively. C1 is a load capacitance connected to the output terminal 4.

Next, the operation will be explained. Assuming that there is no load capacitance C5, the generated output waveform obtained at the output terminal 4 will be as shown in FIG. T11 indicates the period in which the transistor Q is on, and T11 indicates the period in which the transistor Q1 is off. After the TH off period, transition 3
- Q star Q, C5 is on, and transistor Q24 is off. At this time, a current is supplied through the diode D1 and the transistor Q1, half of this current flows through the constant current source 2, and the other half flows through the constant current source 3 and the capacitor C.
Charge in the positive direction.

As capacitor C charges, the emitter potential of transistor Q2 decreases, and its value becomes vcc VDl-vBEQ
When the same V BEQ2 is reached, the transistor Q2゜C4
turns on. However, V is the forward voltage drop of diode D1, ■ is the base-to-emitter voltage of transistor Q4, and vBEQ2 is the voltage between transistor Q2
is the base-emitter voltage of As a result, the transistors Q, Q, and Q5 are turned off, the output terminal 4 becomes low level, and the period shifts to the T1 period in FIG. 4. At this time, diode D
2 and transistor Q2, half of this current flows through constant current source 3 and the other half flows through constant current source 2 to charge capacitor C in the reverse direction. Then, the same operation as described above is repeated, and a rectangular wave oscillation output with a duty ratio of 50% is obtained from the output terminal 4 as shown in FIG.

[Problem that the invention seeks to solve]

Since the conventional oscillation circuit is configured as described above, if the load capacitor C5 is connected to the output terminal 4, even if the transistor Q5 changes from on to off, the charge accumulated in the load capacitor C1 will not be removed. Since the output terminal 4 is gradually discharged through the constant current source 7, the output terminal 4 does not immediately go to a low level, and there is a problem in that the fall of the oscillation output from a high level to a low level is delayed. FIG. 5 illustrates this situation, where T1 is the time determined by the constant current [7] and the load capacitance C5, and T2. T3 is the center level of the oscillation amplitude (Fig. 1
These are the high period and low period of the output as seen by the dashed dotted line).

As shown in the figure, T2≠T3. In this way, in conventional oscillator circuits, when a capacitive load is connected, the duty ratio deviates from 50%, which increases the second-order component in the output frequency component, causing deterioration of the oscillator's output second-order distortion. There was the problem of inviting.

This invention was made to solve the problems mentioned in 1 above, and it is possible to easily improve the output second-order distortion caused by the load capacitance of the output section without changing the circuit configuration from the conventional one. The purpose is to obtain an oscillation device.

[Means for solving problems]

The oscillation device according to the present invention includes first and second transistors that are cross-connected so as to derive oscillation outputs that are in opposite phases to each other by turning on alternately and supplying current; A capacitor connected between the current-drawing side electrodes of the transistor and charged alternately in a forward direction and a reverse direction and defining an oscillation frequency of the oscillation output; and a capacitor having a forward charging time and a reverse charging time different from each other. ,
and duty ratio changing means for changing the duty ratio of the oscillation output so as to reduce output secondary distortion due to the load capacitance of the output section of the oscillation circuit.

[Effect]

The duty ratio changing means in this invention operates to vary the forward charging time and reverse charging time of the capacitor, thereby changing the duty ratio of the oscillation output, so that the oscillation output deviates from 50% depending on the load capacity. By setting the duty ratio changing means in advance so that the duty ratio is corrected, it is possible to reduce the output second-order distortion due to the load capacitance of the output section.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of an oscillation circuit according to the present invention. The circuit of this embodiment is different from the conventional circuit shown in FIG.
Transistors Q, Q7, resistors R, R4 and constant voltage source 8
Different types of constant current consisting of 1. Constant current circuit 9 that flows I2
This circuit is different from the conventional circuit shown in FIG. 3 in other respects. In the configuration of constant current circuit 9, the collector of transistor Q6 is connected to the emitter of transistor Q, and the emitter is grounded via resistor R3. Further, the collector of transistor Q7 is connected to the emitter of transistor Q2, and the emitter is grounded via resistor R4. °Resistances R and R have different resistance values at different constant currents. It is set in advance to flow I2. Transistor Q6゜Q7
The base of is connected to a constant voltage source 8.

Next, the operation of the circuit shown in FIG. 1 will be explained. The basic operation is similar to the conventional circuit shown in FIG. 3, with transistors Q and Q2 being turned on alternately and capacitor C being alternately charged in the forward and reverse directions. At this time, due to the function of the constant current circuit 9,
The forward charging current and the reverse charging current of the capacitor C are different.

That is, in constant current circuit 9, transistor Q6. Q
7 is driven by the same voltage from a constant voltage source 8, but due to the existence of resistors R and R4 with different resistance values, the current 1 flowing through the transistor Q6 and the current 1 flowing through the transistor Q7 is the ratio of the resistors R and R4. It becomes a constant current with different values depending on. When transistor Q1 is on, capacitor C is charged in the positive direction by current I2 flowing through transistor Q7, and when transistor Q2 is on, capacitor C is charged in the reverse direction by current 11 flowing through transistor Q. Since 11≠I2, the charging currents of the capacitor C in the forward direction and in the reverse direction are different.

On the other hand, transistor Q1. The emitter potential threshold for Q2 to turn on is CC'D2 'BEQ3.
'BEQ1 Oyohi vCC' DI-■BEQ4-V
BEQ2 (however, V Dl , V t+2 diode D1.D2 (7) Forward voltage drop, VBEQ1 to V
BEQ4 is the base-emitter voltage of the transistors Q1 to Q4), which have the same value. Therefore, transistor Q1. In order for Q2 to turn on alternately, capacitor C must be charged by an equal amount of charge alternately in the forward and reverse directions. However, since the forward charging current and the reverse charging current are different as mentioned above,
The forward charging time and the reverse charging time do not match, and have a predetermined ratio set by the values of the resistors R and R4.

Figure 2 illustrates this situation, where TH is the positive charge time (during this period, the transistor Q1 is on;
Transistor Q2 is off and output terminal 4 is at high level),
(2) is the reverse charging time (during this period, the transistor Q1 is off, the transistor Q2 is on, and the output terminal 4 is at a low level). As mentioned above, T1 is the constant current source 7
This is the time determined by the current and load capacitance C. T11
The timing is selected so that the high period T2 and low period T3 of the output as seen from the center level of the oscillation amplitude (dotted chain line in the figure) are equal, and this setting is performed by resistors R and R. In this way, by correcting the duty ratio of the oscillation output, which deviates from 50% due to the load capacity C1, to 50% in terms of the center level of the oscillation amplitude, it is possible to reduce the output secondary distortion due to the load capacity C1. .

In addition, in the above-mentioned embodiment, the forward charging current and the reverse charging current are
The forward charging time and reverse charging time of the capacitor C were made to differ by making the currents different, but this can be changed, for example, by the values of the resistors R and R2, the diode D,
By changing the number of connected transistors Q1. Emitter potential ryAla for Q2 to turn on
It is also possible to change the forward charging time and the reverse charging time of the capacitor C while keeping the forward charging current and reverse charging current equal as before, and in this case as well, the above implementation can be performed. It has the same effect as the example.

〔Effect of the invention〕

As explained above, according to the present invention, the duty ratio of the oscillation output is corrected by a simple method of differentiating the forward charging time and the reverse charging time of the capacitor that defines the oscillation frequency. Since the structure is designed to reduce the output second-order distortion caused by the load capacitance, there is almost no need to change the circuit configuration compared to the conventional one. There is.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is an oscillation output waveform diagram according to the invention, Fig. 3 is a circuit diagram showing a conventional oscillation circuit, and Fig. 4 is a diagram showing the load capacitance of the output section. FIG. 5 is a conventional oscillation output waveform diagram when there is no load capacitance at the output section. In the figure, Q and Q2 are transistors (first and second
transistor), C is a capacitor, and 9 is a constant current circuit (
(duty ratio changing means). Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) First and second transistors that are cross-connected so as to derive oscillation outputs with opposite phases to each other by alternately turning on and supplying current, and current deriving sides of the first and second transistors. A capacitor connected between electrodes and charged alternately in the forward and reverse directions and defining the oscillation frequency of the oscillation output, and a capacitor whose forward charging time and reverse charging time are different, An oscillation circuit comprising: duty ratio changing means for changing the duty ratio of the oscillation output so as to reduce output secondary distortion due to load capacitance of the output section.