JPS63114248A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to form a dielectric film uniformly so as to have high insulating property, by forming a transfer gate with a word line, which is embedded in a groove, and the side region thereof, and providing the dielectric film in contact with the surface of a source or a drain region on the side of the surface of the gate. CONSTITUTION:In a groove 17 formed in a semiconductor layer, a word line W is embedded. A transistor Tr for a transfer gate is formed with the word line W and the side surface region of the word line. A source 12 or a drain region 11 of the transistor Tr is made to be one electrode on the side of the surface of the semiconductor layer. A capacitor C having a dielectric film 15 is formed in contact with the surface of the regions 11 and 12. Thus a memory cell is constituted. Since the oxide film 15 of the capacitor can be formed by thermal oxidation of a silicon layer 16, the uniform, highly reliable dielectric film is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor integrated circuit device, for example, a dynamic RAM (random access memory) having a memory cell consisting of one transistor and one capacitor.
This is related to ``Mory''.

4. Prior Art A conventional dynamic RAM normally has a transfer gate transistor T in the word line, as shown in FIG.
The gate electrode of r is connected, and a capacitor C is formed between its drain region and power supply Vcc.

On the other hand, as shown in FIG. 3, the position of the capacitor C is opposite to that in FIG.
A memory cell that exists between the source region of ' is proposed. Such a memory cell can also operate as a dynamic RAM.

As a dynamic RAM with the circuit configuration shown in FIG.
As shown in the figure, the N+ type expansion i (regions 1 and 2) of the transistor Tr' formed in the P type epitaxial layer 6 is
(that is, the source region 2) is connected to LOCO3 (Local Oxidati) by the second layer polysilicon wiring 3.
on of 5 silicon) is led out on the oxide film 4, and in this lead-out region, a capacitor C' is formed with the thin oxide film 5 as the dielectric film and the third layer polysilicon pit line B as the other electrode. Are known. Note that W in the figure is the first layer polysilicon word line.

The structure shown in FIG. 5 is called a stacked cell, and a capacitor C' is formed between both polysilicon layers 3-B.
This is a thin oxide that acts as a capacitance 1]! J5
There is a problem with insulation properties, and dielectric breakdown is likely to occur. Moreover,
The manufacturing process for such cells is complex.

OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device comprising a memory cell that has a uniform and highly reliable capacitor and is easy to manufacture.

20 Structure of the Invention That is, in the present invention, a word line is embedded in a trench formed in a semiconductor layer, and a transfer gate transistor is formed by this word line and its side region,
and a semiconductor integrated circuit device in which a source or drain region of the transistor is used as one electrode on the surface side of the semiconductor layer, and a capacitor having a dielectric film is formed in contact with the surface of the region, thereby forming a memory cell. This is related to.

E, Example The present invention will be explained in detail below.

Figures 1 to 3 show the dynamic RAM according to this embodiment.
This figure shows a memory cell.

In this memory cell, a linear groove 17 is formed through the P-type epitaxial layer 16 grown on an N-type semiconductor substrate 11 in the thickness direction, and a thin gate oxide film 18 is inserted into the groove. A polysilicon word line W is embedded. Then, use this word line as a gate,
An N+ type source region 12 and a drain region 1 are provided in the side region.
1. A vertical transfer gate transistor Tr formed with a channel region 19 is provided. On the surface side of the epitaxial eyebrow 16, a capacitor C is formed, with the source region 12 of the transistor Tr serving as one electrode and the true B serving as the other electrode. Note that the substrate 11, which is also a drain region, is set at the power supply Vcc level.

This memory cell is illustrated isometrically as shown in FIG. Note that in FIG. 2, the N+ type diffusion region 12 under the bit line B is formed by the mask pattern 12 used at the time of ion implantation.
The LOCO3 oxide film 14 is shown in a shape corresponding to
also has a masking effect, so the ion implantation region is
This results in a shape pattern that approximately corresponds to region 12 in the figure.

If the memory cell is constructed as described above, the oxidation 11*15 of the capacitor can be formed by thermal oxidation of the silicon layer 16, resulting in a uniform and highly reliable dielectric film. This oxide film can be easily grown using a normal F8 oxidation process. Furthermore, there is no difficulty in the process when using a film other than the thermal oxide film.

Also, although the word line W was buried in the trench 17, the trench 1
Since 7 is linear, manufacturing is relatively easy compared to other shapes. Then, the side surface of the trench 17 is connected to a transistor Tr.
Since it is used as a region, the cell size can be significantly reduced in plan view, and the manufacturing process can also be simplified.

Although the present invention has been illustrated above, the above-mentioned example can be further modified based on the technical idea of the present invention.

For example, the materials, formation methods, patterns, etc. of each region and layer described above may be changed in various ways. In addition to 5i02, other high dielectric constant films such as TiOx, WOx, Si3N4, etc. can be used as the dielectric film. Furthermore, the conductivity type of at least a portion of the semiconductor region described above may be reversed.

9. Effects of the Invention As described above, the present invention is characterized in that a transfer gate is formed by the word line embedded in the trench and its side regions, and a dielectric film is provided in contact with the surface of the source or drain region on the front surface side of the gate. Because of this structure, this dielectric film can be formed uniformly and with high insulation properties by thermal oxidation, etc., which increases reliability.In addition, since the word line is buried in the trench and the gate is formed as described above, the cell size can be reduced. It can be downsized and the manufacturing process can be simplified.

[Brief explanation of the drawing]

1 to 3 show embodiments of the present invention, in which FIG. 1 is a sectional view of a memory cell portion of a dynamic RAM, FIG. 2 is a plan view of the main part of FIG. 1, and FIG. is an equivalent circuit diagram of a memory cell. 4 and 5 show conventional examples, in which FIG. 4 is an equivalent circuit diagram of a memory cell portion of a dynamic RAM, and FIG. 5 is a sectional view of a memory cell portion of another dynamic RAM. In addition, in the symbols shown in the drawings, 11... Semiconductor substrate (drain region) 1
2... Source region 15... Dielectric film 16... Epitaxial layer 17...
...Groove 18...Gate oxide film Tr...Transfer gate C...
. . . Capacitor B . . . Bit line W . . . Word line.

Claims (1)

[Claims] 1. A word line is embedded in a trench formed in a semiconductor layer, a transfer gate transistor is formed by this word line and its side region, and the source or drain region of the transistor is connected to one side on the surface side of the semiconductor layer. A semiconductor integrated circuit device in which a capacitor is formed as an electrode and has a dielectric film in contact with the surface of the region, thereby forming a memory cell.