JPS63113729A - Ic card - Google Patents

Abstract

PURPOSE:To obtain a coding/decoding table of such a size that can complicate satisfactorily the explanation by making use of a CPU processing program itself as a coding/decoding table. CONSTITUTION:A CPU 11 produces a cryptogram to transmit the program of the CPU 11 itself stored in a program memory 13 to a reader/writer 20 as a coding/decoding table and also decodes the cryptogram received from the reader/writer 20. The reader/writer 20 stores the program of the CPU 11 for an IC card 10 into a data memory 24 as a coding/decoding table in order to decode the cryptogram received from the card 10 and to produce the cryptogram to be sent to the card 10. Thus it is possible to obtain a coding/decoding table of such a size that can complicate satisfactorily the explanation since said table can be set over the entire memory area of the memory 13.

Description

[Detailed description of the invention] (Industrial application field) This invention relates to an IC card.

(Prior art) In recent years, information processing systems using IC cards (hereinafter referred to as t
C card system) has been developed. here,
As is well known, an IC card is a card made of synthetic resin or the like, and has a semiconductor assembly (4 circuits) such as a microprocessor and memory embedded therein.

Since IC cards are superior to magnetic cards in terms of storage capacity and information processing ability, it is expected that they will be used for various information processing instead of magnetic cards in the future.

By the way, when information processing using an IC card requires a high level of security, it is necessary to restrict usage rights and encrypt data, as in normal information processing.

Conventionally, when setting encryption/decryption functions to an IC card, the encryption/decryption table is set to C as shown in Figure 14.
The configuration was such that it was incorporated as a data statement in the PU control program.

However, since there is a physical limit to the memory capacity of an IC card, having an encryption/decryption table as described above reduces the usable area for the user. Problems arose such as the difficulty of setting up tables of sufficient size to complicate the problems and explanations.

The latter problem can be solved by using the R8A method, which is a public key Meigetsu encryption method, and the DES method, which is a symmetric encryption method.
Considering the processing power of current CPUs used in C cards and the capacity of supporting RAM, it must be said that the feasibility of this is extremely low.

(Problems to be Solved by the Invention) This invention was made to deal with the above-mentioned circumstances, and it does not affect the usable memory area, and the R8A method and D
To provide an IC card capable of setting an encryption/decryption table of sufficient size to make explanation difficult without adopting a method such as the ES method that imposes a burden on a CPU.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides, for example, a CPU
The processing program itself is used as an encryption/decryption table.

(Function) According to the configuration in which the CPU program itself is used as an encryption/decryption table as described above, if necessary, the table can be set over the entire storage area of the program memory, so You can get a table of any size.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an IC card system using an IC card according to one embodiment. In the figure, 10 is an IC
20 is a reader/writer that forms an interface between this IC card 10 and a computer (not shown).

In the IC card 10, 11 is a CPU that performs information processing with the reader/writer 20.

12 is a data buffer that temporarily stores the processing results of the CPU 11; 13 is a program memory that stores programs for the CPU 11; 14 is a data memory, 15
is an I10 port, and 16 is an address data bus.

Similarly, in the reader/writer 20, 21 is a CPU,
22 is a data buffer, 23 is a program memory, 24
is a data memory, 25.26 is an I10 port, and 27 is an address data bus.

The CPU 11 uses the CPU 11 program stored in the program memory 13 as an encryption/decryption table to create a ciphertext to be transmitted to the reader/writer 20, and decrypts the ciphertext sent from the reader/writer 20. do.

Note that the reader/writer 20 stores the IC card 1 in the data memory 24 in order to decrypt the cipher text sent from the IC card 10 and create a cipher text to send to the IC card 10.
The program of CPU 11 of 0 is stored as an encryption/decryption table.

Here, while referring to the flowchart in FIG.
An example of the encryption processing of the card 10 will be described in detail.

In step S1 of FIG. 2, the CPU 11 reads the IC card-specific parameter X1 from the data memory 14 and holds it. Note that this unique parameter x1 may be, for example, a secret code number.

In the next step S2, the CPU 11 takes in and holds the random number RND. As this random number RND, for example, the date of that day can be used.

In the next step S3, cpui'+ generates a public lKp from the unique parameter xi and the random number RND. This public key Kp is also stored at a predetermined address in the data buffer 12. The generation function in this case needs to be a function that can be inversely transformed.

As such a function, for example, a logical sum function as shown in the following equation (1) can be used.

Kp = Xi EXORRND... (1)
In the next step S4, the CPU 11 converts the random number RND into a read address ADR of the program memory 13.

This conversion is performed, for example, by the following formula 4 formula % This formula (2) is 2
An example will be shown in which the pig string written at address 55 is used as an encryption/decryption table.

In step S5, the CPU 11 writes the plaintext P (data length LNG) to be output into the data buffer 12, using A1 as the write start address.

In the next step S6, cpuil sets the offset address 0FST to O.

In the next step S7, the CPU 11 reads 1 byte of plaintext P from the address (A1+0FST) on the data buffer 12. Further, the CPU 11 reads data T from address ΔDR on the program memory 13. Then, this data T is used to encrypt the plain text P.

This means that the plaintext P1 has been encrypted by bytes.

The above encryption is also performed according to an inversely transformable function. An example thereof is shown in the following equation (3).

E-P EXORT... (3) Here, E is a ciphertext.

In the next step S8, the CPU 11 transmits the ciphertext E and the public key Kp to the reader/writer 2o.

In the next step S9, the CPU 11 increments the offset address 0FST by 1.

In the next step 51C), the CPU 11 subtracts the offset address 0FST from the data length LEN of the plaintext P.

In the next step 811, the CPU 11 performs step S1
Determine whether the subtraction result S of 0 is O or not, and if it is not O,
Returning to step S7, the next byte is encrypted. If the subtraction result S is O, it means that all bytes of the plaintext P have been encrypted, and the encryption process is ended. In this encryption process, the read address of the data buffer 12 is updated by incrementing the offset address, and the read address of the program memory 13 is updated according to a predetermined rule starting from ADR, which will be described in detail later. It has become so.

FIG. 3 shows the logic of the CPU 11 for performing the above encryption. In the figure, 111 is a public key generation logic that generates public IK+1 from the unique parameter)] and random rXIRND according to equation (1) above. 112 is a random number/address conversion logic that converts the random number RND into the read address ADR of the program memory 13 according to the above equation (2). 113 is an encryption logic that reads data from the encryption/decryption table according to the read address ADR and encrypts the plaintext P.

The transmitted text X transmitted to the reader/writer 20 has a public key Kp in the header section and a ciphertext E in the data section.

The encryption process for the IC card 10 is performed as described above. The ciphertext obtained by this process is
The data is decrypted by the CPU 21 of the writer 20 according to the encryption/decryption table stored in the data memory 24. This decryption process is almost the same as the process in which the IC card 10 decrypts the ciphertext E sent from the reader/writer 20 to the IC card 10. Therefore, in the following explanation, the decoding process will be explained on the IC card 10 side.

FIG. 4 is a flowchart showing the decryption process on the IC card 10 side. The transmission text X sent from the reader/writer 20 is stored in a predetermined area of the data buffer 12. In step S1 of FIG. 4, the CPU 11 reads out the public key Kp from the address where the public key Kp is stored in this area and holds it.

In the next step S2, the CPU 11 selects the data memory 1.
The unique parameter X1 is read from 3 and held.

At the next step S3, cpu"+i is set at step S1
A random number RND is obtained from the public key Kp read out in step S2 and the unique parameter x1 read out in step S2 according to the following equation (4).

RND-Kl) EXORXi -------・(4)
In the next step S4, the CPU II converts the random number RND into the read address ADR of the program memory 13 according to the above equation (2).

In the next step S5, the CPU 11 sets the offset address FST to O.

In the next step S5, the CPU 11 reads data T from the address (A2+0FST) on the program memory 13.

In the next step S7, the CPU 11 reads out 1 byte of ciphertext E from the address (A2+0FST) of the data buffer 12, and uses this ciphertext E and the data T read out in step S6 according to the following equation (5). Calculate plaintext P.

P-E EXORT... (5) Note that A2 above indicates the address where the first byte of the encrypted text E is stored in the data buffer 12 where the transmitted text X is stored.

In the next step S8, the CPU 11 writes the 1-byte plaintext P obtained in step S7 to the address (A2+0FST) on the data buffer 12.

In the next step S9, C, PUll increments the offset address 0FST by 1.

In the next step S10, CPLJll performs step S10.
In step S7, it is determined whether the data read from the data buffer 12 is end of text (ETX), and if it is not end of text (ETX), step S6
Returning to , the next bye 1- of the ciphertext E is decrypted. On the other hand, if it is end-of-text (ETX), this means that all bytes have been decoded, so the process is terminated.

FIG. 5 is a block diagram showing the logic of the CPU 11 for decoding. In the diagram, 114 is public 1! Random number RN according to equation (4) from Kp and unique parameter x 1
This is the random number generation logic that generates D. Further, 115 is a decryption logic that decrypts the ciphertext E and obtains the plaintext P.

FIG. 6 shows, for example, the encryption process of the IC card 10 and the decryption process of the reader/writer 20 when the IC card 10 is the sending side. Further, the seventh factor schematically shows the data in the program memory 1. FIG. 7 shows a 16-bit program memory.

In addition, in the example of FIG. 6, the random number RND is 6D in hexadecimal (
Therefore, according to the above equation (2), the read address ADR of the program memory 13 becomes DA(H).

As described above, in this embodiment, the program itself of the CPU 11 is used as an encryption/decryption table (see FIG. 8). According to such a configuration, if necessary, the encryption/decryption table can be set over the entire storage area of the program memory 13, so it is possible to set a table of sufficient size to make explanation difficult. 1q is possible. Incidentally, FIG. 8 shows the data stored in the program memory 13 of this embodiment along with FIG. 14 described above.

By the way, in FIG. 7, in order to read the data T of the data length LEN of the plaintext P from the program memory 13,
Although the case where adjacent addresses are sequentially read from the first read address ADR has been shown, reading may be performed as shown in FIGS. 9 to 11, for example. What is shown in Figure 9 is
The read address is updated according to an arithmetic progression (arithmetic progression 4). In the example shown in FIG. 10, the read address is updated according to a geometric progression of 2n. In the system shown in FIG. 11, the read address is updated using a random number series expressed by the following equation (6).

T I −T +Fi (RNDxlo)+1・
...(6) In this way, the confidentiality of the program can be improved.

In addition, in the previous embodiment, the ciphertext E is obtained by taking the exclusive OR of the data T read from the program and the plaintext P.
For example, as shown in Figure 12, 8-bit arithmetic processing is used to add data T to plaintext P, or as shown in Figure 13, data T is added to plaintext P. “1′ of T.

Of course, it is also possible to use a bit transposition process that inverts the bit corresponding to the bit.

Furthermore, in the previous embodiment, a case has been described in which the data T read from the program memory is used for the information transmitted to the reader/writer 20 to create the ciphertext E, but the invention is not limited to this, for example. Of course, the data read from the program memory may be transmitted as the encrypted text E as it is.

[Effects] As described above, according to the present invention, it is possible to make explanations difficult without reducing the usable memory area and without adopting methods that place a burden on the CPU, such as the RAS method or the DES method. It is possible to provide an IC card in which an encryption/decryption table of sufficient size can be set.

[Brief explanation of the drawing]

FIG. 1 is a configuration lock diagram of an IC card system shown for explaining the configuration of an embodiment of the present invention, and FIGS.
The figure is a diagram for explaining the configuration and operation of one embodiment.
1 to 13 are diagrams shown to explain main parts of different embodiments of the present invention, and FIG. 14 is a diagram shown to explain a conventional configuration. 10...IC card, 11...CPU, 12...
Data buffer, 13...Program memory, 14.
...Data memory, 15...I10 boat. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 5 Figure 4 Figure 10 Encryption processing of card 10 Figure 6 Figure 8 Figure 14 Figure 9 Figure 10 Figure 11 8 bit arithmetic processing浬 ■Hex notation I TJ & NC decoding) Bit conversion d processing/21i! Illustration 13 of Joki

Claims (1)

[Claims] The program itself for information processing is used as an encryption/decryption table, and based on this table, it creates a ciphertext to be transmitted to an external device, and also decrypts the ciphertext sent from the external device. An IC card characterized by being configured.