JPS63111547A - Memory control system - Google Patents

Abstract

PURPOSE:To realize the debug of a microprogram having no break instruction by utilizing a detecting function using redundant bits as a detecting function of a break point for debug of software. CONSTITUTION:A memory 8 stores previously a program to be debugged and the error checking redundant bits are added to this program for each read/write access given from a processor 1. These redundant bits are stored in a parity memory 7. A parity detecting circuit 4 detects the parity of the redundant bits of the memory 7. While the 2-bit parity control registers 5 and 6 are added and the left and right members of both registers 5 and 6 serve as two outputs of different multiplexers 12. Then the read/write state of the memory 7 is controlled by the output of the multiplexer 12.

Description

TECHNICAL FIELD The present invention relates to a memory serial control system, and more particularly to a memory control system for program debugging in a data processing device.

When debugging software in conventional data processing equipment, d3 uses a break instruction for fetch stops, or uses a logic analyzer or in-circuit emulator for machine language systems such as microprograms that do not have break instructions. There are two methods:

Further, in the case of read/write access stop, there is only a method using a logic analyzer or an in-circuit emulator.

When debugging software in the conventional data processing device mentioned above, a disadvantage is that other than performing fetch stop using a language system that has break instructions, it is necessary to use other equipment such as a logic analyzer or in-circuit emulator. There is.

Purpose of the Invention The present invention utilizes a detection function using redundant bits, which are error check bits, as a breakpoint detection mechanism for software debugging. The purpose of the present invention is to provide a memory control method that enables debugging of programs such as J3 without using devices such as logic analyzers and in-circuit emulators.

According to the present invention, there is provided a memory control method in which a redundant bit for error checking is added to each access unit of a program and written to the memory, and the redundant bit is checked in response to a memory read instruction. a redundant bit changing means capable of changing the contents of the redundant bit according to a predetermined rule; and a control for writing the redundant bit changed and set by the redundant bit changing means into a memory and reading the written redundant bit. redundant bit readout and damage means for reading out the redundant bits, and checking means for checking the read redundant bits, the redundant bits at a predetermined address of the memory are read out, the redundant bit changing means changes the redundant bits, and the redundant bits are changed by the redundant bit changing means. A memory control system 1q is characterized in that the redundant bits are checked while writing to a predetermined address and sequentially controlling the execution of programs stored in the memory.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a practical example of the present invention, in which the memory 8
A program to be debugged is stored in advance in the program, and a redundant bit for error checking is added to this program for each read/write access unit from the processing unit 1. This redundant bit is used for parity. Memory 7 is full.

The parity generation circuit 3 has the ability to generate an even parity, and its generated output is directly inputted to the multiplexer 9 and is inverted by the inverter 31 to become odd parity, which becomes another input to the multiplexer 9. This multiplexer 9 connects the output of the flip-flop 2 and its inverter 21.
The flip-flop 2 is controlled by an inverted output from the processing device 1, and the flip-flop 2 is set by a command from the processing device 1.

The parity detection circuit 4 has the ability to perform parity detection on the redundant bits of the parity memory 7, and can notify the processing device 1 of the detection result via the AND gate 10. The gate signal of this AND gate 10 is the output of the multiplexer 11, and whether or not the parity detection result is notified to the processing device 1 is controlled depending on the state of this gate signal.

On the other hand, parity control registers 5 and 6 each having a 2-bit configuration are provided, and the bits on the left side of both registers are used as the two inputs of the multiplexer 11. Further, the sixth bit of both registers 5 and 6 is controlled by another multiplexer 12, and the read/write state of the parity memory 7 is controlled by the output of this multiplexer 12.

Both multiplexers 11 and 12 are controlled by read/write commands from the processing device 1, and inverters 111 and 121 are provided corresponding to the multiplexers 11 and 12, respectively, in order to invert these read/write commands. There is.

Flip-flop 2 is 1? If set to the state ``0'', the parity generation circuit 3 functions to generate odd parity, and if the flip-flop 2h is set to ``0'', it functions to generate even parity. Further, when the processing device 1 instructs a read operation, the contents of the parity control register 5 (for read) are enabled by the multiplexers 11 and 12, respectively, and if the left-hand bit of the contents is 1'', The output of the parity detection circuit 4 is notified to the processing device 1 via the AND gate 10, and O1
In the case of 1, no notification is given because the AND gate 10 is closed. When the right-hand bit of this register 5 is 1, the redundant bit is read from the parity memory 7, and when it is 0'', the redundant bit is written to the memory 7.

When the processing device 1 instructs a write operation, the contents of the parity control register 6 (for write) are validated by the multiplexers 11 and 12, and are controlled in the same way as when instructing the read operation described above. .

FIG. 2 is a flowchart showing the operation procedure of the blocks in FIG. 1, and is a flowchart using an example of access stop for debugging a program stored in the memory 8 in advance. In this flowchart 1~, each content of the 2-bit parity control register 5.6 is set to (x, y).
The left term X indicates whether parity detection is checked or not, and is represented by symbols C and N, respectively. Further, the sixth term y is either written into the memory or read, and each is represented by the symbol W.

Represented by R.

In step 21, flip-flop 2 is set to "1" so that parity generation is odd parity generation. Then, in step 22, the read parity control register 5 is set to (N, R), and the parity memory 7 is placed in a read mode state while the parity detection result is not notified to the processing device 1. In step 23, in this state, a redundant bit corresponding to the break address that should be a breakpoint is read out according to the address specification from the processing device 1, and the redundant bit is converted to odd parity by the parity generator set to generate odd parity. Change settings. After that, step 24
The write parity control register 6 is set to (N, R), and the redundant bits changed to odd parity are rewritten to the same address in the memory 7 in response to a write instruction from the processing device 1.

After that, in step 25, both registers 5 and 6 are set to <N, R), and the following step 26 is performed.
In steps 29 to 29, the type of access stop is determined.

In the case of a read access stop, the read parity control register 5 is set; in the case of a write access stop, the write parity control register 6 is set; and in the case of a read/write access stop, both registers 5 and 6 are set (C).

R).

Under this setting, as shown in step 30, the memory 8
When the program to be debugged stored in the debugged program is sequentially executed, when attempting to access the memory contents stored at the address previously set as a break address, the parity detection circuit has set it to odd parity. Redundant bits are detected. This is notified to the processing device 1 via the AND gate 10, and a breakpoint interrupt can be generated. This results in
It is possible to know that control has passed to that address, and it can be used for debugging, which is program verification.

Effects of the Invention As described above, according to the present invention, by using the conventional parity error detection function using redundant pins as a detection function for software debugging, microprograms etc. that do not have break instructions can be This has the effect that debugging can be easily performed without using special equipment such as a logic analyzer or an in-circuit emulator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the present invention in detail, and FIG. 2 is a flowchart showing the operation of FIG. 1. Explanation of symbols of main parts 1...Processing device 2...Memory

Claims (1)

[Claims] A memory control method in which redundant bits for error checking are added and written to memory for each program access unit, and the redundant bits are checked in response to a memory read instruction, the contents of the redundant bits being A redundant bit changing means that can be changed according to a predetermined rule; a redundant bit reading/writing means that writes the redundant bit changed and set by the redundant bit changing means into the memory and reads and controls the written redundant bit; and checking means for checking the redundant bits at a predetermined address of the memory, the redundant bits at a predetermined address of the memory are read out, changed by the redundant bit changing means, and written again to the predetermined address of the memory. A memory control method characterized in that the redundant bits are checked while sequentially controlling the execution of stored programs.