JPS63107317A - Counter circuit - Google Patents

Abstract

PURPOSE:To realize high speed operation by constituting a reset signal of a shift register for clock count so as to be an output of the final stage of the said register thereby decreasing the delay due to feedback. CONSTITUTION:The shift register 1 consists of n-set of D-FFs (D flip-flop) DFi(i=1, 2,..., n). A 2-input NOR gate 2 receives an output Q1' of a 1st stage DF1 and an output Qn of a final stage DFn. An AGj(j=1, 2,..., n-1) is a 2-input AND gate receiving an output Qj+1 of the DFj+1 and the output Qj of the DFj. Suppose that outputs Qi of all the D-FF DFi are all logical '0' at the initial state, then '1' is always fed to the data input D1 of the D-FF DF1 of the first stage and every time one clock pulse Cp comes from the initial state, the output Qi goes to '1' sequentially from the output Q1. When the output Qn goes to 1 at the n-th pulse, since they are reset pulses to all the D-FF DFi-DFn, all the outputs Qi to to '0' and the state is restored to the initial state. The operation above is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention counts the number of input pulses, and when a given number has been counted, starts counting from l again. 3...) relates to the counter circuit.

[Prior Art] FIG. 5 is a circuit diagram of a conventional n-ary counter circuit shown in, for example, "All About Digital ICs" by Yoshio Shirato (Tokyo Denki University Press, 1982). In,
1 is a shift register for clock counting consisting of n D flip-flops (hereinafter referred to as D-FF) DFi (i=1°2,...p n), and 5 is a NOR (NOf?).
) is a gate.

Next, the operation will be explained. In the following explanation, it is assumed that all D-FFs are positive edge φ triggers and are reset by the reset signal @1''. Figure 6 shows the time chart of this n-ary counter circuit. This counter circuit consists of n D-FF DFi (
Shift register 1 is configured with i=1.2, -n), and when the outputs Qi of <<n-1) D-FFs excluding the final stage are all "0", the first stage D-FF DFI By adding 61″ to the data input terminal D1 of n
This is to obtain a forward counter operation.

Now, if all D-FF DFi are reset with a reset signal and the output Qi is set to "0" (Qi is the Q output of DFi), the output of the NOR gate 5 becomes "l" and D
41m is added to the data input terminal Ds of -FF DFI. This "■" sequentially shifts to the right every time the clock pulse Cp is input.

When any of the outputs Q1 to Qn-1 is ``1'', the output of the NOR gate 5 is 0'', so only the Q output of one D-FF is ``1'', which is then shifted to the right. When the nth clock pulse CP occurs, the final stage o D
-F F D F n (D Q output Qn is @1”
Since all others are 0''', the output of the NOR gate 5 becomes wlm, 11'' is again added to the data input terminal D1 of the first stage D-FDFDF1, and the same operation is repeated thereafter.

[Problem that the invention seeks to solve]

Since the conventional n-ary counter circuit is configured as described above, the minimum operating clock cycle of this counter circuit is #
There is a problem in that the minimum operating clock cycle of the D-FF is greater than that of the D-FF by the propagation delay time of the Bonoa gate 5, and its maximum operating frequency is also lower than that of the D-FF.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a high-speed counter circuit that can operate up to the maximum operating frequency of a D-FF.

[Means for solving problems]

The counter circuit of the first invention according to the present invention includes n (n
=1,2. A shift register is constructed with flip-flops of Stage (1" l + 2 + "' * "-1
) and (i+1) stage, and between the outputs of the first and final stage flip-flops, a logical operation circuit with n stages performs n
It is designed to output a decimal counter output.

The counter circuit of the second invention according to this invention comprises m (2
A first shift register is configured with flip-flops (, m < n - 1), the input of the first stage flip-flop of this first shift register is fixed to @l'', and the output of the final stage flip-flop is The reset pulse for each of n flip-flops is passed through a delay circuit, and the i-stage and (i+1)
A logical operation circuit of (m-1) stages performs a logical operation between the outputs of flip-flops of stages ('=l*2e...t''-t) to output a (m-1) base counter output, In addition, a second shift register is constituted by a (n-m-1) stage flip-flop whose first stage input is one of the outputs of this (m-1) stage logic operation circuit, and this second shift register The outputs of the flip-flops in each stage of the shift register are output as the remaining counter outputs.

[Function] The shift register in the first aspect of the present invention has its input fixed at ``1'' and shifts this to the subsequent stage sequentially every time a clock is input, so that the final stage output is @1''. When this occurs, the signal is reset to return to the initial state, and this process is repeated to perform pulse counting.

Further, the first shift register in the second invention of the present invention transfers "l" in the same manner as the shift register in the first invention, and when the final stage becomes @l, this signal is delayed. It is reset by a reset pulse to return to the initial state, and by repeating this, pulse counting is performed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the first invention of the present invention. In the figure, 1 indicates n D-FF DFi (i=1
．． 2. ...+n) shift register, 2 is the first stage D-FF DFI output Q1 and the final stage D-FF
A two-person gate with the output Qn of DFn as the input.
Gj (j=1.2, -, n-1) is a j-stage D-FF
Output Qj of DFj and D-FF'DFj of (j+i) stage
This is a two-man AND gate whose input is the output Qj+x of +x.

Next, the operation of this first invention will be explained.

FIG. 2 shows a time chart of the counter circuit according to the first invention. Now, the initial state is Heteno D-F.
It is assumed that the outputs Qi of F DFi (i=1, 2, . . . , n) are all "0"K.

The data input D1 of the first stage D-FF DFl is always “
1'' is added, each time the clock pulse Cp increases by one from the initial state, the output Qi sequentially becomes @1'' starting from the output Ql, as shown in FIG. Output Q at nth shot
When n becomes “1”, this is the D-FF DF
Since it is a reset pulse for i to DFn, all outputs Q
i becomes @0'' and returns to the initial state.This process is repeated υ.

The counter output At (i=t, 2p-n) is A i
= Q i■Qi+t (1=L2*”'*” 1
) +■；IAn = Qn + Ql
Since it is a double sweep OR, the counter output Ai has a pulse width of 1/foL as shown in Figure 2.
x (foLx is the repetition frequency of the clock pulse CP), a pulse train with a repetition frequency foLx/n,
A pulse train identical to the output Qi of the conventional n-ary counter circuit shown in FIG. 5 is obtained.

FIG. 3 shows an embodiment of the second invention of the present invention.
First shift register composed of FF DFi (i=1.2, .-, m), 31d (n-m+1) o D
-FF DFm+1% DF n+t The second shift register 4 is a delay circuit with a delay time τ. The rest is the same as in Figure 1. In this counter circuit, the reset pulse is not taken from the final stage output Qn of the n-stage shift register 1 as shown in FIG.
-FF DFm output Qm (-n -1 for 2<=m)
From the beginning, it is assumed that the number of stages of the first shift register 1 is m. The embodiment shown in FIG. 1 operates when the pulse width W of the reset pulse is smaller than the clock period 1/fOLK, but the embodiment shown in FIG. 3 operates when the reset pulse width W is 1/fOLK. It operates when the value is approximately equal to or greater than /fOLK. FIG. 4 shows a time chart of this counter circuit. here,
m= n −2, l/foLx<-W≦2/fOLK
The case is shown below.

The first shift register 1 operates exactly the same as the shift register 1 in FIG. 1 until the mth clock pulse CP is issued.
Counter output At (t=1 +2 *….

m-1) can be obtained in the same manner. In other words, “ ” Q
t ” Qi+1 (””1 e2 s...rml
) is given by At the m-th clock pulse Cp, Qm=
@l”, but all D-FF DF
i (i=1.2, =-, m) is reset.

At this time, if fOLK is high and the clock cycle is smaller than the reset pulse width W determined by the rise and fall times of the D-FF, the output Qm of the m-stage D-FF DFm, that is, the reset pulse ⇒ is equal to one clock cycle ( 1/ fat
, x) or more. Therefore, the number of stages m of the first shift register 1 is delayed so that the falling edge of the reset pulse R is between the falling edge of the nth clock pulse Cp and the rising edge of the (n+1)th clock pulse Cp. Adjust the delay time τ of circuit 4. As a result, from the (m+1) clock pulse CP to the n-th clock pulse CP
During the period, the output Q i (r = i p 2 p..., m) is “
0", counter output"(i" l * 2,
"・+ n'l l ) is also 0". During this period, the counter output Am-1 is converted into a second
input to shift register 3, counter output Am-1
By sequentially shifting υ counter output AJ (
Then, when the (n+1)th clock pulse CP is input, the reset signal hole is already at "O", so Q1="l" is obtained again. ”, and the above operation is repeated.

In addition, in the above two embodiments, the counter output Ai
In the embodiment of the first invention, Ai=Qt-Qi+
t (i=t e2*-pn-x), An=Qn-Ql
, in the embodiment of the second invention, A i engineering Qi −Q i
+ t(!= 1, 2.=-, m-1), Aj =
DR(Am-t) (j”mtm+1,---,n
; 几=j−m+l; DR(A) is a signal obtained by delaying A by 几 clock], but Qi・Qi−t C'=
l*2+...p''-1 (Fig. 1), i=l.

2 p ””*m-1 (Figure 2)] as Qi■Qi+t
get the same result.

It goes without saying that the delay circuit 4 may be unnecessary depending on the phase difference between the clock pulse CP and the output Qm.

〔Effect of the invention〕

As described above, according to the first invention, since the reset signal of the shift register for clock counting is configured to be the final stage output of this register, the delay due to feedback is extremely small, and the conventional feedback system can be gated. There is also an advantage that a counter with an inserted one operates at high speed.

Further, according to the second invention, the first shift register for clock counting is configured with a number of stages smaller than the desired count number, and the final stage output of the first shift register is used as the delay of the flip-flop that configures the first shift register. Since the first shift register is configured to be reset with a delay taking into account the rising and falling times and the number of counts, the maximum operating frequency of the flip-flops constituting the first shift register is A counter that can operate up to

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a counter circuit according to an embodiment of the first aspect of the present invention, FIG. 2 is a time chart thereof, and FIG.
FIG. 4 is a circuit diagram of a counter circuit according to a second embodiment of the present invention, FIG. 4 is a time chart thereof, FIG. 5 is a circuit diagram of a conventional counter circuit, and FIG. 6 is a time chart thereof. . 1 is a clock count shift register, 2 is an OR gate, 3 is a second shift register, 4 is a delay circuit, 5 is a NOR gate, DFi (t=ly2p...n) is a D7 lip, AGj (j= 1, 2
,-. n-1) is an and gate. In addition, in the figures, the same reference numerals indicate the same or similar parts. Patent applicant Mitsubishi Electric Corporation -〇Figure 2 03 r--[-I-- A3-Go 8-11! Ear ya An-+-1-ya, J'- An-1←←Yo1-1←- Figure 4 A3--Go] Ya 1111''-To 〶11〇----9 -1'' on -m- and 1190 cll:

Claims (2)

[Claims] (1) Counting the number of input pulses in n-ary (n=1, 2,
3), the counter circuit is composed of n stages of flip-flops, the input of the flip-flop in the first stage is fixed to "1", and the output of the flip-flop in the final stage is the output of the flip-flop in each stage. A shift register is used as a reset signal, and the output of the flip-flop in the previous stage and the output of the flip-flop in the succeeding stage in the shift direction of the shift register are input, and the flip-flop in the final stage receives the output of the flip-flop in the last stage. outputs a counter output by inputting the output of the flip-flop and the output of the first-stage flip-flop, respectively.
A counter circuit comprising a stage logic operation circuit. (2) Counting the number of input pulses in n-ary (n=1, 2,
3...) counter circuit, m stages (2≦m≦n-1
), the input of the flip-flop in the first stage is fixed to "1", and the output of the final stage is passed through a delay circuit and serves as a reset signal for the flip-flops in each stage. and outputs a counter output by inputting the output of the flip-flop in the previous stage and the output of the flip-flop in the succeeding stage which are forward and backward in the shift direction of the first shift register (
m-1) stages of logic operation circuits, and a second flip-flop consisting of (n-m+1) stages in which one of the outputs of the logic operation circuit is input to the first stage and the output of each stage is used as a counter output. A counter circuit equipped with a shift register.