JPS6310623B2 - - Google Patents
Info
- Publication number
- JPS6310623B2 JPS6310623B2 JP56141388A JP14138881A JPS6310623B2 JP S6310623 B2 JPS6310623 B2 JP S6310623B2 JP 56141388 A JP56141388 A JP 56141388A JP 14138881 A JP14138881 A JP 14138881A JP S6310623 B2 JPS6310623 B2 JP S6310623B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- run
- circuit
- input
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141388A JPS5842336A (ja) | 1981-09-07 | 1981-09-07 | クロック信号発生回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141388A JPS5842336A (ja) | 1981-09-07 | 1981-09-07 | クロック信号発生回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5842336A JPS5842336A (ja) | 1983-03-11 |
| JPS6310623B2 true JPS6310623B2 (pt) | 1988-03-08 |
Family
ID=15290829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56141388A Granted JPS5842336A (ja) | 1981-09-07 | 1981-09-07 | クロック信号発生回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5842336A (pt) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02156740A (ja) * | 1988-12-09 | 1990-06-15 | Victor Co Of Japan Ltd | 光情報伝送装置 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001069129A (ja) | 1999-08-31 | 2001-03-16 | Mitsubishi Electric Corp | 受信装置及び通信システム |
-
1981
- 1981-09-07 JP JP56141388A patent/JPS5842336A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02156740A (ja) * | 1988-12-09 | 1990-06-15 | Victor Co Of Japan Ltd | 光情報伝送装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5842336A (ja) | 1983-03-11 |
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