JPS63105098U - - Google Patents
Info
- Publication number
- JPS63105098U JPS63105098U JP19746086U JP19746086U JPS63105098U JP S63105098 U JPS63105098 U JP S63105098U JP 19746086 U JP19746086 U JP 19746086U JP 19746086 U JP19746086 U JP 19746086U JP S63105098 U JPS63105098 U JP S63105098U
- Authority
- JP
- Japan
- Prior art keywords
- program
- memory
- timer
- confirmation
- shot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
Description
第１図は本考案のプログラムタイマー装置の一
実施例を説明するブロツク図、第２図は従来のプ
ログラムタイマー装置のブロツク図である。
１１…入力処理回路、１２…プログラム設定用
メモリ、１３…プログラム確認用メモリ、１４…
メモリ切換回路、１６…表示回路。
FIG. 1 is a block diagram illustrating an embodiment of the program timer device of the present invention, and FIG. 2 is a block diagram of a conventional program timer device. DESCRIPTION OF SYMBOLS 11...Input processing circuit, 12...Memory for program setting, 13...Memory for program confirmation, 14...
Memory switching circuit, 16...display circuit.
Claims (1)
ログラム及びプログラムモードの設定や、確認モ
ードの設定及び入力データのコントロールを行な
う入力処理回路と、 この入力処理回路で設定したタイマープログラ
ムを記憶する第１のメモリと、 この第１のメモリに設定された単発プログラム
のタイマー動作が終了した時にその単発プログラ
ムの設定データが転送されるプログラム確認用の
第２のメモリと、 前記第１のメモリに単発プログラムが設定され
かつ前記入力処理回路に確認モードが設定された
とき、タイマー動作完了の前後状態に対応して前
記第１のメモリと前記第２のメモリを切り換え、
確認表示するデータを表示回路へ出力するための
メモリ切換手段とを具備したことを特徴とするプ
ログラムタイマー装置。[Scope of claim for utility model registration] An input processing circuit that has a key input function and a clock function, and that sets the timer program and program mode, sets the confirmation mode, and controls input data; a first memory for storing a timer program; a second memory for program confirmation to which the setting data of the single-shot program is transferred when the timer operation of the single-shot program set in the first memory is completed; When a one-shot program is set in the first memory and a confirmation mode is set in the input processing circuit, switching between the first memory and the second memory in accordance with the state before and after completion of the timer operation;
A program timer device comprising memory switching means for outputting data to be displayed for confirmation to a display circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19746086U JPS63105098U (en) | 1986-12-24 | 1986-12-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19746086U JPS63105098U (en) | 1986-12-24 | 1986-12-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63105098U true JPS63105098U (en) | 1988-07-07 |
Family
ID=31157219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19746086U Pending JPS63105098U (en) | 1986-12-24 | 1986-12-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63105098U (en) |
-
1986
- 1986-12-24 JP JP19746086U patent/JPS63105098U/ja active Pending
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