JPS6310444B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control device that performs bit arithmetic processing and data processing at high speed.

A conventional device of this type is shown in FIG. In the figure, 1 is an oscillator, 2 is a program counter that increments every oscillation period of the oscillator, and 3 is a sequence control program memory. 4 is a bit arithmetic unit, and 5 is a temporary storage memory for bit arithmetic operations. 6 is an input section, 14a to 14f
is an input terminal. 7 is an output section, 15a~
15f is an output terminal. Reference numeral 8 represents a word operation means for executing data processing, and 9 represents a system program memory for this word operation means. 20 is the output line of the program counter, 21 is the word calculation means 8
(microprocessor) address bus, 22 is a data bus. Reference numeral 23 is a gate control line connected to the interrupt input of the word calculation means and the switching gates 10 to 13, etc. 24 is a gate switching request line; 25 is a sequence control program memory address line;
26 is a data line. 27 is a command input line to the bit arithmetic unit 4, 28 is an address designation line for a temporary memory memory output from the bit arithmetic unit 4, and 29 is a temporary memory memory 5 for temporarily storing input information, output information, and operation information. This is the address line. 30 is a data line of the temporary storage memory, and 31 is a data line from the bit arithmetic unit 4. A first address switch 10 switches between the program counter output and the address bus of the word calculation means 8. 11
is a first data switch which connects the data line of the sequence control program memory 3 to the data bus of the word calculation means 8 or the bit calculation means 4. Reference numeral 12 denotes a second address bus switch, which switches the address designation line 28 from the bit arithmetic unit 4 and the address bus of the word arithmetic means 8. 13
is a second data switch, which switches the data line of the temporary storage memory for bit operations to the data bus of the bit operation unit 4 or the word operation means 3. FIG. 2 is a program example for explaining the operation of FIG. 1, and FIG. 3 is an operation timing diagram. FIG. 2 40a is the first
This is the step instruction word and contains a bit operation instruction. 40c is the third step instruction word, which contains a word operation instruction. 40h is an instruction indicating the end of a series of programs. Figure 3 4
1 indicates the operation timing of the bit arithmetic unit 4. During the "L" period, a command word is applied from the sequence control program memory 3 to the bit arithmetic unit 4, and during the "H" period, the bit arithmetic operation is executed. Reference numeral 43 indicates memory access timing during word operation.

Next, the operation will be explained. The constant frequency signal output by oscillator 1 increments program counter 2. The output lines of each stage of the program counter 2 pass through the first address switch 10, and the address of the sequence control program memory 3 is incremented at every position as the program counter 2 increments. The contents of the sequence control program memory 3 are sequentially read out through the data line. The stored contents of the sequence control program memory 3 are a mixture of bit operation instructions and word operation instructions as shown in FIG. given to 4.
In the example of FIG. 2, the instruction code 40a is given during the "L" period of timing 42, and the "H"
During the period, through the input terminal 14 and the input section 6,
Bit operations are performed between the input information read by the word operation means 8 and previously written in the temporary storage memory 5, between the output information in the temporary storage memory 5, etc. Next, the program counter 2 increments and the instruction 40b is applied to the bit arithmetic unit 4. Similarly, an operation is performed between the contents written in the temporary storage memory 5 and the operation result inside the bit operation unit 4.

40c by next program counter increment
The word operation instruction code is applied from the sequence control program memory 3 to the bit operation unit 4 via the sequence control program memory 11. The bit operation unit 4 detects that the instruction code is a word operation and interrupts the word operation means 8 via the gate control line 23. At the same time, the word operation detection line is connected to the oscillator 1, the switches 10, 11,
12 and 13, and connects the sequence control program memory 3 and the word calculation means 8, and the temporary storage memory 5 and the word calculation means 8. Then, the word operation means 8 accesses the memory at the timing shown in FIG. 343. During this time, bit operations are completely stopped. When the word operation is completed, the bit operation unit 4 releases the gate control line 23 by the gate switching request line 24, restarts the oscillator 1 for bit operation, and switches the gates 10, 11, 12,
13 to its original state and resumes bit operations.

In the case of monitoring to check whether a specific instruction code is included in the sequence control program, the gate switching request line 24 is sent from the word operation means 8.
A signal is issued to the gate control line 23 to stop the bit operation, and the address line of the sequence control program memory 3 is connected to the address bus 21 and data bus 22 of the word operation means 8.

Then, whether a specific instruction code is stored in the sequence control program memory 3 or not is checked by sequentially reading out the sequence program memory 3. If a specific instruction code is found, a signal is sent to the gate switching request line 24, and the operation of the oscillator 1 and the switching of the gates 10, 11, 12, and 13 are restored to their original state using the gate control line 23, and the bit operation is restarted. do.

Conventional sequence control devices are configured as described above, so in addition to stopping bit operations during word operation processing, it is also necessary to stop operations during monitoring, so it takes time to execute all instructions. There were other drawbacks.

This invention was made to eliminate the drawbacks of the conventional ones as described above, and uses a control circuit consisting of two counters and a flip-flop to determine the timing of completion of execution of one bit operation instruction by the first counter. is detected, the second counter sets the timing for the word operation means to access the memory, and the flip-flop controls the increment of both counters, so that the word operation means can access the sequence control program memory and the temporary memory. The bit operation is paused only when the storage memory is accessed, and when the word operation means accesses the system program memory, the bit operation can be executed. It is an object of the present invention to provide a sequence control device that can minimize the pause period and shorten the calculation cycle.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 4, 50 is a counter that generates a first Gray code (alternating binary code), 51 is a counter that generates a second Gray code, 52 is an input gate of the first Gray code counter, and 53
is the input gate of the second Gray code counter, 5
Reference numeral 4 designates a bit operation timing decoder which inputs the output line 62 of each stage of the counter 50 and outputs the timing of the bit operation to the timing input line 64 of the bit operation unit 4. A first decoder 55 decodes the output of each stage of the counter 50 and controls the flip-flop group 58. A second decoder 56 decodes the output of each stage of the counter 51 and controls the flip-flop group 58.
59 is an output line for the first oscillation pulse generated by the oscillator 1, and 70 is an output line for the second oscillation pulse. The first number of oscillation pulses is higher than the second number of oscillation pulses.

60 is the input line of the first Gray code counter;
61 is an input line of the second Gray code counter, and 63 is an output line of each stage of the second Gray code counter. 66 is the output line of the second decoder;
Reference numeral 71 denotes an address decoder, which generates a control signal 58 on the output line 67 of the address decoder only when the word operation means 8 accesses the sequence control program memory 3 or the bit operation temporary storage memory 5.

A switch control decoder 57 controls a switch control line 68. Reference numeral 69 is a control line for controlling the gates 52 and 53.

FIG. 5 is a timing diagram illustrating the operation shown in FIG. 4.

59a is the signal waveform of the first oscillation pulse output line 59, 62a, 62b, 62c is the output waveform of each stage of the output line 62 of each stage of the first Gray code counter, and 64a, 64b is the signal waveform of the bit operation timing decoder 54. In the waveform of the output line 64, 64a is the program read timing from the sequence control program memory 3, and 64b is the bit operation execution timing. 65a is the waveform of the output line 65 of the first decoder, and 67a is the waveform of the address decoder output line 67. If there is an access request to the memories 3 and 5, the waveform 67a becomes "H". 6
3a, 63b, and 63c are the outputs of each stage of the counter 51 that generates the second gray code, and 68a
is the output of the decoder 57, which causes the switch 1
0, 11, 12, and 13, and connects the address bus and data bus of the sequence control program memory 3 or temporary storage memory 5 to the word operation means 8. Reference numeral 66a represents the waveform of the output line 66 of the second decoder, which resets the flip-flop group 58 and connects the bit calculation means, the sequence control program memory 3, and the temporary storage memory 5.

Next, the operation will be explained.

The constant frequency signal output by the oscillator 1 is applied to the input gate 52 of the program counter 2 and the first Gray code counter 50. In this example, the frequency applied to the first oscillation pulse output line 59 is about four times higher than the frequency applied to the second oscillation pulse output line 70. Initially 10,
Switches 11, 12, 12, etc. are on the bit operation side, and the output from each stage of the program counter 2 drives the address line of the sequence control program memory 3 via the first address switch 10. , sequence control program data is applied to the bit calculator 4 via the switch 11.
On the other hand, the first oscillation pulse is given to the Gray code counter 50 via the gate 52, and 62a, 62
Waveforms such as b and 62c are generated at each stage of the counter. The bit operation timing decoder 54 is 64
Generate timing signals such as a and 64b, and
The instruction code is read from the sequence control program at timing 4a, and the bit operation is executed at timing 64b. If a request for monitoring to read out the contents of the sequence control program or input/output information written in the temporary storage memory arises, the word calculation means 8 will read out the contents of the sequence control program or read out the input and output information written in the temporary storage memory. An address signal for accessing the memory 5 is sent to the address bus 21. address decoder 7
1 outputs a waveform signal like 67a to the output line.
When the signal of 67a is "H" and the signal of 65a is "H", the flip-flop group 58 is controlled and the gate control line 69 is set to "L" to close the gate 5.
At the same time as closing the gate 2, the gate 53 is opened. As a result, the second Gray code counter 51 starts to advance, and a pulse like 68a is sent to the output 68 of the decoder 57.
Reference numerals 2 and 13 connect the address lines and data lines of the sequence control program memory 3 and the temporary storage memory 5 to the address bus 21 and data bus 22 of the word operation means 8, so that the word operation means 8 can read out the memory. executed. The end of the read execution is detected by the second decoder 56 and sends a pulse 66a to the flip-flop group 58, which initializes the flip-flop group 58 and resumes incrementing the first Gray code counter 50. When the word operation instruction code is detected by the bit operation unit 4, the gate control line 23 is used to stop the program counter 2 from advancing, control the switches 10, 11, 12, and 13, and start the word operation means 8. , makes the sequence control program memory 3 accessible, reads the parameters of the word operation command, and executes the word operation. At this time, determine the type of word operation,
If it is OK to start the bit operation of the next step, send a bit operation start signal to the gate switching request line 24, switch the switches 10, 11, 12, and 13 to their original states and restart the bit operation. . In this case, word operations and bit operations are performed in parallel. In this process, if the word operation means 8 needs to process the data in the temporary memory 5, the address of the temporary memory 5 is sent to the address bus 21, and the address decoder 71 detects this and sends the address decoder output line 67 to 67a. The flip-flop group 58 is controlled at the timing 65a, the step of the first Gray code 50 is stopped, and the step of the counter 51 that generates the second Gray code is started. timing 68
a is sent to the switching devices 10, 11, 12, 13, and the word operation means can access the temporary storage memory 5.

In the above embodiment, counters that generate Gray codes are used as the counters 50 and 51, but the counters 50 and 51
A general binary counter may be used for this purpose. In this case, erroneous pulses caused by uneven rising and falling edges of the signals at each stage of the counter can be eliminated by changing the operation of the bit arithmetic unit 4 to a synchronous logic circuit. It has the same effect as the example.

As described above, according to the present invention, when the word operation means is necessary, it interrupts the timing of the bit operation unit and accesses the memory.
To execute the monitoring function, it is only necessary to stop the bit operation means to a minimum, and it is also possible to execute bit operations and word operations in parallel, which has the effect of shortening the operation cycle. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional sequence control device, FIG. 2 is an explanatory diagram showing an example of a program for explaining the operation of FIG. 1, FIG. 3 is an operation timing diagram, and FIG. 4 is an example of the present invention. A block diagram showing the sequence control device according to the embodiment, and FIG. 5 is an operation timing diagram of FIG. 4. In the figure, 3 is a second storage means (sequence control program memory), 5 is a first storage means (temporary storage memory), 4 is a bit calculation means (bit calculation unit), and 50 is a first counter (first 51 is a second counter (a counter that generates a second Gray code); 55 is a counter that generates a second Gray code;
is the first decoder, 56 is the second decoder, 58
is a flip-flop group. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1 bit calculation means, storage means for storing input information, output information, and calculation temporary storage information, second storage means for storing a sequence control program, and generating execution timing of the bit calculation means. a first counter, a word operation means for performing data processing, a second counter for generating timing such that the word operation means accesses the first storage means or the second storage means; The flip-flop group is controlled by a counter and the output of the second counter, and the flip-flop group is controlled by the request from the word operation means and the output of the first counter. The word operation means accesses the first or second storage means by stopping the increment of the first counter and starting the increment of the second counter, and the word operation means accesses the first or second storage means; The sequence control device is characterized in that the flip-flop group is set to an initial state by the output of , the first counter is restarted, and the second counter is stopped. 2. The sequence control device according to claim 1, wherein a counter that generates a Gray code (alternating binary code) is used as the first counter and the second counter.