JPS6310398A - Access system for two-port memory - Google Patents

Abstract

PURPOSE:To attain a quick access without waste time by applying an independent access that is split into two parts and an interleave access method to a memory with >=4 banks. CONSTITUTION:A memory control circuit 12 controls a dynamic RAM11 composed of four banks 110-113 by control signals REQ, ACK and ADDRESS to a A port 13A and a B port 13B. Buffers 14A1, 14A2, 14B1 and 14B2 are provided between the dynamic RAM11 and the ports 13A, 13B. Data in the banks 110, 111 is exchanged through the buffers 14A1, 14B1, and data in the banks 112, 113 through the buffers 14A2, 14B2. By classifying the banks into a group of banks 110, 111 and that of banks 112, 113, the memory control circuit 12 gives signal WE and addresses and accesses the banks at every two banks. Here the banks are accessed by the interleave method, whereby an access without waste time due to precharging is attainable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-port memory access method, and particularly to a dynamic RAM access method.

B0 Summary of the Invention The present invention enables high-speed access in a 2-port memory with four or more punctures by separating the memory into two parts and making each part accessible independently and in an interleaved manner. This is what I did.

C0 Prior Art Conventionally, two-port memory systems using dynamometer RAM as memory often have the configuration shown in FIG. 3, with four punctures 10 to 1. The memory control circuit 2 gives an acknowledgment AOK to the memory access request REQ from the A port 3A and the B port 3B to the Dynazutsuta RAMI consisting of Address strobe signals RAS and 0Afl are applied to the dynamic RAM 1, and data gate control signals are applied to the buffers 4A and 4B to control data writing or reading between the address memory element corresponding to the address data and the corresponding port. This is done via 4B.

With such a configuration, when the memory control circuit 2 allows memory access from one port, it denies access to requests from other ports. In addition, dynamic RAM 1f is used as memory.
For use, the matrix address strobe signal RA8,
Precharge time is secured for access by OA8.

D2 Problems to be Solved by the Invention In the conventional memory access method, there is a problem in that while one port is accessing the memory, the other port cannot access it. In addition, the precharge time required in Dynat ivy memory results in longer cycle times for access times. Therefore, when accessing a puncture that has been accessed widely, waste time including precharge time is required, and the access time becomes longer. FIG. 4 shows a time chart of a read cycle. When A port 3A# subsequently B port 3B issues a memory access request, the RA corresponding to B port is On the other hand, the OA generates 8 signals, increasing the dead time for requests from the B port.

As a countermeasure against this problem, there has conventionally been an interleaving method in which by changing the puncture to be accessed during sequential access, another puncture is accessed in place of the puncture being precharged.

However, the interleaving method is effective only when one port accesses continuously and sequentially, and in a two-port memory where two ports access randomly, the lr (interleaving method) is Even by law, access by one party is prohibited while the other party is accessing it, so the effect of reducing wasted time is small.

Means and operation for solving the E0 problem The present invention has been made in view of the above problem, and it separates a memory having four or more punctures into two parts, each of which can be accessed independently, and has two ports. configured so that data can be exchanged between the two ports, and access requests from the two ports are processed in separate punctures using an interleaving method;
Separated notes are accessed from both ports using an independent interleaving method to eliminate wasted time and provide high-speed access.

? ,Example FIG. 1 is a circuit diagram showing one embodiment of the present invention.

4 hanks 11°~11. Dynamic RA consisting of
For M11, the memory control circuit 12 sends a control signal RII! to M port 13A and B port 13B#. Q, A OK, ADDRK8B performs memory control. Dyna Yo Tsuku RAM
11 and port 13A.

There is a buffer between 13B and 14A□14 At #1
4 Bts 14 Bm are provided, and the data of puncture 11° and 111 is stored in buffer 14A.

Transferred and received via 14Bs-p, Bank llt, Ll
The data of s is exchanged via the buffer 14Aw*14B1.

Memory control circuit 12 G-! ,ノ(nk t1
0s11tto11t -IIm ξζWl! 1
A signal, AI) DRFf8S is provided to enable access to each of the two divided banks, and data gate control is provided via the two banks.

In such a configuration, when one bank is accessed by the first port, the other bank can also be accessed from the second port, and the other bank is accessed from each port. This allows access without wasting time due to pre-charging time.

For example, 13mm is bank 11°, 11. B port 13B while accessing using the interleave method.
Banks IIs and l1m are accessed using an interleave method. FIG. 2 illustrates a time chart of a read cycle according to the method of the present invention.
13 This is a case where B accesses the punk 11th while accessing the bank 11°.

Note that when both the A port and the B port access a bank that is not separated, for example, llo and 11+, they wait until the access of one side is completed, but if both ports access different banks at this time, for example, 11
When accessing ゜A port), xi, and B port respectively, it is sufficient to secure only the precharge time by the effect of interleaving.

Therefore, by separating four banks into two and performing interleaved access between the two banks, when both ports access separate nodes or separated banks, the conventional As shown in FIG. 4 or FIG. 5, high-speed access can be performed without wasting time.

Specifically, A port 13 A is the main (!M.

If B port 13 B is a DMA device such as a disk, data and programs are transferred from the disk to banks 11□11. while the main OP'U is executing programs in banks lla and 11+. can be loaded into. At this time, the access to 0PTT and the disk is performed sequentially, so that the effect of interleaving appears, eliminating the wasted time of precharging, and since each access is performed in separate banks, the waiting time for each is easily eliminated. Allows the fastest access possible. This access method becomes more effective under operating systems that support virtual memory.

Effects of the G0 Invention As described above, according to the present invention, since the memory having four or more banks is accessed separately into two, independent access and interleaved access are performed, simultaneous access by two ports is possible. Moreover, the interleaving method enables high-speed access with no wasted time.

Special feature: Dynamic RAM-based two-port memory enables high-speed access without precharging time.

[Brief explanation of drawings]

FIG. 1 is a 2-port memory circuit diagram showing one embodiment of the present invention, FIG. 2 is a time chart illustrating the read cycle of FIG. 1, FIG. 3 is a conventional 2-port memory circuit diagram, and FIG. 4 is a conventional read cycle time chart, and FIG. 5 is a conventional read cycle time chart using the interleave method. 11...Dynamic RAM % 12...Memory control circuit, 13A, 1313...Port, 1
4A1, 14 A! , 14 Bt e14B1・
·buffer.

Claims (1)

[Claims] A memory having four or more banks is divided into two, each of which is configured to be independently accessible and data can be exchanged between two ports, and access requests from the two ports are handled by an interleaving method. A two-port memory access method characterized by performing access processing within separate banks.