JPS63102263A - Thin film semiconductor device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film semiconductor device, that is, a semiconductor device formed by sequentially laminating thin film semiconductor layers, insulating layers, etc. on a substrate such as glass.

[Prior art]

In recent years, thin film semiconductor devices have been developed, that is, a semiconductor layer made of amorphous silicon or the like is placed on a substrate made of glass, aluminum, etc.

2. Description of the Related Art Semiconductor devices formed by laminating insulating layers and the like have been put into practical use. This thin film semiconductor device 1 is suitable for use in solar cells, liquid crystal display drive devices, etc., which require a large area.

In particular, an amorphous silicon thin film field effect transistor using a SiNx layer as a gate insulating film has excellent switching characteristics, and is therefore optimal as a driving device for the above-mentioned liquid crystal display.

In other words, in the past, CRT displays capable of high-definition, high-brightness, color display were mainly used as display devices for displaying images such as television monitors and data display devices, but CRT displays are smaller and lighter. In addition, flat panel displays are attracting attention as low power consumption and high quality display devices. For example, the above-mentioned liquid crystal display is common as a flat panel display, and its driving methods include a simple matrix driving method and an active matrix driving method. Among these, the active matrix driving method independently drives and controls each pixel composed of three primary colors.
Since each pixel can be driven with relatively high power,
It is possible to increase the contrast ratio.

Now, thin film transistors using amorphous silicon as driving devices for liquid crystal displays as mentioned above can be made larger in area and lower in cost, and have a large on/off current ratio, making it possible to use capacitors placed in parallel with the liquid crystal layer. This is preferable since there is no need to correct the capacitance.

Figure 4 shows conventional amorphous silicon containing hydrogen (a-3i:
FIG. 2 is a schematic diagram showing the structure of a field effect transistor as a thin film semiconductor device using H).

One surface of the a-5i:l semiconductor layer 5 with a film thickness d is silicon nitride (
A gate electrode layer 1 is provided with an insulating layer 4 such as SiNx or silicon oxide (S i Ox) interposed therebetween. Furthermore a-
A source electrode layer 2 is provided at both ends of the length L of the 5i:l semiconductor layer 5, and a drain electrode layer 3 is provided at the other end.

Such a thin film transistor has a positive (
+) When a gate voltage VG of
A charge 7 is induced by the capacitance WC between the :H semiconductor N5 and the gate electrode layer 1. This induced charge 7(-
C・VG) is a-5i in length due to the drain voltage VD applied between the source electrode layer 2 and the drain electrode layer 3.
:)1 Passes through the semiconductor layer 5. In this way, drain current 8 (10) controlled by gate voltage VG and drain voltage VD flows.

Furthermore, it is conceivable that a current that is not controlled by the gate voltage VG, that is, a leakage current 6 flows in the a-3i:)l semiconductor layer 5, but since the a-3t:)l semiconductor layer 5 has a high dark specific resistance, The leakage current 6 is considered to be negligible.

Now, amorphous silicon containing hydrogen (a-5
Thin film transistor (TFT: Thi
nFilm Transistor) is not formed on a silicon wafer of a limited size as in the past, but is formed using plasma CVD (Chemical Vapor
It can be manufactured by a CVD method or other CVD method. For this reason, liquid crystal displays using TPT have the following advantages: as mentioned above, it is possible to increase the area, and it can be manufactured in a relatively low-temperature process of about 30°C.
-3i:l The semiconductor layer 5 has a high dark specific resistance, in other words, a low dark conductivity, which eliminates the need for a charge storage capacitor (specifically, the capacitor arranged in parallel with the liquid crystal layer described above), which simplifies the manufacturing process. This method has advantages such as being simple and being able to continuously form an insulating layer, an active layer, etc. in the same reaction chamber.

[Problem that the invention seeks to solve]

By the way, in order to improve the performance and stability of a thin film semiconductor device W using amorphous silicon, the film quality of the amorphous silicon layer that is the active layer and the SiNx or SiOx film that is the insulating layer is an important factor. Needless to say. However, in addition, an insulating layer and an active layer (semiconductor layer made of amorphous silicon)
It has been reported that the characteristics of the interface with the material also have a large effect. In other words, amorphous silicon has its energy gap (
There are continuous localized levels in the forbidden band (forbidden band), which reduce the mobility (runability) of carriers, that is, charges induced in the amorphous silicon semiconductor layer. In addition, if SiNx or SiOx as an insulating layer is not dense, porous, or has vacancies, this may cause the amorphous silicon semiconductor layer and gate electrode layer that are located through the insulating layer to Since the induced charge during this period cannot be controlled, a drift may occur in the capacitance component.

By the way, the operation of a TFT using amorphous silicon mainly utilizes the induction and movement of carriers due to the electric field effect along the interface between the insulating layer and the active layer.
If there are many interface states, that is, if the density is high, these will act as electron trapping levels, reducing field effect mobility and further reducing the stability and reliability of the drain current.

In addition, it has been pointed out that amorphous silicon thin film semiconductor devices have problems with operational stability, particularly that fluctuations in dark value voltage (dark value shift) are relatively large. The reason for this is that because the insulating layer and the amorphous silicon layer as the active layer are heterojunctions, there are many defect levels at the junction interface, and when the insulating layer is formed of SiNx, the stoichiometric Due to the theoretical misalignment, localized levels exist in the insulating layer, and since these are close to the electron or hole mobility edge of the amorphous silicon layer, there is no non-local level when a positive gate voltage is applied. Electrons are injected from the crystalline silicon layer into the insulating layer, and holes are injected from the amorphous silicon layer into the insulating layer when a negative gate voltage is applied, and these charges cause a dark value shift. is thought to occur.

Although the amorphous silicon thin film semiconductor device is made of amorphous material, the insulating layer is SiNx or SiOx.
Since the energy gap between the active layer and the amorphous silicon layer of the active layer is very different, and the magnitude of the film stress generated during the deposition of each layer is also different, it is reasonable to assume that strain occurs at the bonding interface between the two. be. Furthermore, since there are excessive hydrogen atoms on the surface after SiNx or SiOx is formed, when an amorphous silicon layer as an active layer is further stacked on top of SiNx or SiOx, these excess It is thought that hydrogen rings are incorporated into the amorphous silicon film and cause defects to occur at the interface. It is believed that such defect levels existing near the interface are a cause of greatly impairing the stability and reliability of the amorphous silicon thin film semiconductor device, as described above.

In order to reduce the density of defect states caused by such interface states, for example, the film formation method may be changed, or the insulating layer and the amorphous silicon layer as the active layer may be formed in different chambers. By doing so, we prevent contamination due to excess hydrogen atoms as mentioned above, and by strictly controlling the manufacturing process of insulating layers such as SiNx or SiOx, we prevent defects in the insulating layer. Countermeasures can be considered. However, the former method has poor reproducibility and is therefore difficult to supply products of stable quality, and the latter method requires high temperatures for film formation, so it is difficult to provide products with stable quality. There is a great possibility that the layer will be destroyed.

The present invention has been made in view of the above circumstances, and is an object of the present invention to prevent a decrease in carrier mobility caused by localized levels when amorphous silicon containing hydrogen is used as an active layer, and to An object of the present invention is to provide a thin film semiconductor device that prevents deterioration of semiconductor characteristics due to defect levels existing at the interface between an insulating layer and an amorphous silicon layer and improves stability.

[Means for solving problems]

In the thin film semiconductor device of the present invention, by interposing an impurity layer mainly composed of silicon to which impurities are added at the interface between the semiconductor layer made of amorphous silicon containing hydrogen and the amorphous insulating layer, amorphous silicon The movement of electrons or holes from the semiconductor layer to the insulating layer is prevented, thereby suppressing the occurrence of dark value shift.

The present invention provides an N-film semiconductor device having a structure in which a hydrogen-containing amorphous silicon semiconductor layer and an amorphous insulating layer are bonded together. It is characterized by interposing an impurity layer in which an element of Group 1 or Group 2 is added to the silicon layer as an impurity element.

[Effect]

In the thin film semiconductor device of the present invention, an impurity layer interposed at the interface between an amorphous silicon semiconductor layer containing hydrogen as an active layer and an insulating layer, specifically, a p or p+ type impurity layer is added to the amorphous silicon containing hydrogen. Alternatively, a layer doped with n- or C-type impurities suppresses the injection of electrons or holes from the amorphous silicon semiconductor layer containing hydrogen, which is the active layer, into the insulating layer, thereby preventing the dark value shift from occurring.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 shows a transistor (hereinafter referred to as TFT: Th1n Fi1m↑rans) as a thin film semiconductor device according to the present invention.
1. istor).

In the figure, 200 is a glass substrate. This glass substrate 200
A gate electrode layer 201 is patterned thereon, and an insulating layer 204 made of, for example, silicon nitride (SiNx) or silicon oxide (SiOx) is formed to cover the gate electrode layer 201. And the conventional T
In the case of PT, a semiconductor layer is formed on this insulating layer 204, specifically a semiconductor layer of amorphous silicon containing hydrogen (a-3i:
In the present invention, an impurity layer 213 is once formed on the insulating layer 204, and then the above-mentioned a-3i:H semiconductor layer 20 is formed on this impurity layer 213.
5 is formed.

In other words, the insulating layer 204 and the a-3t:H semiconductor layer 20
This means that an impurity \tA layer 213 is interposed between it and 5. Then, on the a-3i:H semiconductor layer 205, n
+ type a-3t: A source electrode layer 202 and a drain electrode layer 203 are formed with a suitable length spaced apart with a +1 layer 212 interposed therebetween.

Note that 211 in the figure is a protective film for protecting the a-3t:H semiconductor layer 205 from external impurity ions, moisture, etc. by blocking it from the outside world.

Each layer constituting the above-mentioned thin film transistor of the present invention will be explained in more detail below.

It goes without saying that the insulating layer 204 is required to have high resistance, that is, high insulation, but it is also required to have high breakdown voltage.

Therefore, the insulating layer 204 is, for example, S I N x +S
Materials such as iOxNy and Ta205 are used. Among these, SiNx is suitable because it has excellent environmental resistance and chemical resistance.

To form the insulating layer 204 with silicon nitride (SiNx), a silane-based gas, for example, S
Formed by decomposing a mixed gas of iH4 (monosilane) and nitrogen-containing gas such as NH3 (ammonia), N2, etc. using plasma generated by glow discharge, and stacking the decomposed gaseous atoms on a substrate. do.

Now, as a characteristic of the insulating layer 204, the dark specific resistance is 101
2Ω・1 or more, optical band gap is 2. It is desirable that it is OeV or more. In addition, the film thickness is 1000 to 1
A range of μm is desirable.

Note that although this insulating layer 204 is generally formed of a single layer, one insulating layer 204 is formed by sequentially stacking a plurality of layers.
4 is of course possible, and in such a case, it is considered possible to further improve the film characteristics and quality by considering the combination.

Next, the impurity layer 213, which is a feature of the present invention, is composed of p
or p+ type or n or n+ type a-3t :H
It is formed in When forming p or type 1 a-3i:)I, the raw material gas is silane-based, such as monosilane (Si)! +) and a gas such as diborane (B2H6) containing, for example, boron (B) belonging to group Ⅰ as an impurity dopant, a laminated layer is formed by a plasma CVD method.

When forming the impurity layer 213 with p- or p+-type a-3i:H, the doping amount of the impurity dopant of group (I) elements is usually preferably in the range of 1 x 10-' to 1 atomic %, and more It is preferably in the range of 1 x 10-' to 1 x 10-2 atomic %, in other words, on the order of 10-3 or less.

In addition, the dark specific resistance of p or p+ type a-5i:H is 1
A range of ×108 to lXIO3Ω·1 is desirable, and a range of activation energy of 0.7 to 0.2 eV is desirable. In other words, the impurity layer 213 formed under conditions outside the above-mentioned range does not produce a bronking effect on electrons, or the characteristics as a TPT deteriorate.

On the other hand, impurity layer 2 is formed by n or n+ type a-3i:H.
When forming 13, the above-mentioned p or p+ type a-3t
: It is desirable to have film properties that are almost the same as in the case of H. In this case, as the impurity dopant, a Group I element such as phosphorus (P) is used, and as the gas containing it, for example, phosphine (PH3) can be used.

The amount of impurity doped at this time is usually desirably in the range of 1 x 10-' to 2 atomic %, and 1 x 10-4 to 1 x 1 atomic %.
A range of 0-2 atomic % is more preferred.

The thickness of the impurity layer 213 in these cases is preferably in the range of 1° to 500°, more preferably in the range of 20 to 100°.

The a-3i:H semiconductor layer 205 is an active layer of the TPT of the present invention, and is usually formed in layers by plasma CVD using a silane-based gas, such as monosilane (S i H4), as a raw material gas.

The film thickness of this a-5i:H semiconductor layer 205 is an important factor that influences the TFT characteristics, but it is generally 1' 00
A range of 500 to 3000 people is desirable, and a range of 500 to 3000 people is more preferable.

Next, the n+ type a-3i:8 layer 212 is the source electrode layer 20.
2 and train electrode layer 203 and a-3i:H semiconductor layer 2
The a-5i:H semiconductor layer 205 is interposed between the source electrode layer 202, the train electrode layer 203, and the a-5i:H semiconductor layer 205 in order to improve the electrical contact between the a-5i:H semiconductor layer 205 and the source electrode layer 202 and the train electrode layer 203.

This n+ type a-3i: HIif 212 is produced by plasma CV using a mixed gas of silane-based gas, such as SiH4, and a group V element, such as PH3 containing P, as a raw material gas.
Laminated layers are formed by method D.

The film characteristics of this n+ type a-5i:It layer 212 are as follows:
It is necessary to dope the impurity dopant to the extent that it has sufficient n+ type characteristics. Therefore, the dopant content is 1 x 10-5 to 2 atomic%,
The dark specific resistance ranges from 1 x 108 to 1 x 102 Ω.
The activation energy is preferably in the range of 0.7 to 0.2 eV. The film thickness is preferably in the range of 100 to 1000 people, more preferably in the range of 200 to 500 people.

Furthermore, the protective layer 211 is a-5i:I+ semiconductor layer 205
It is necessary to protect the TPT characteristics, stabilize the TPT characteristics, and improve reliability, and should be formed with the same insulation characteristics as the insulation layer 204 described above. The thickness of the protective layer 211 is preferably in the range of 100 to 5,000 people, more preferably in the range of 500 to 3,000 people.

Finally, source electrode 1i202 and drain electrode layer 2
03 is usually formed by vacuum bonding or electron beam bonding. The material is formed by laminating any one of chromium (Cr), nichrome (Nz-Cr)+aluminum (A/), titanium (Ti), etc., or by sequentially laminating a combination of these materials.

These source electrode layer 202 and drain electrode layer 203
Generally, the appropriate film thickness is about 1000 people.

Note that the gate electrode layer 201 may also be formed in the same manner as the source electrode layer 202 and drain electrode layer 203 described above.

In the thin film transistor of the present invention having such a configuration, unlike the conventional thin film transistor, an impurity layer 213 is interposed between the a-3i:H semiconductor layer 205, which is an active layer, and the insulating layer 204.

This impurity layer 213 is p or p+ type a-S
i: In the case of 8 layers, when a positive gate voltage VG is applied to the gate electrode layer 201, the p or p-type impurity layer 213
acts to suppress injection of electrons induced at the interface between the insulating layer 204 and the a-Si:H semiconductor layer 205 into the insulating N2O4. That is, the impurity layer 213 is considered to function as an electron blocking layer.

Specifically, the blocking effect of this impurity layer 213 can be considered as follows. Conventional simply insulating layer 204 and a-
In the structure in which the 5i:H semiconductor layer 205 is simply bonded, the insulating layer 204 made of nitride and the a
-3i: Due to the difference in physical properties from the II semiconductor layer 205,
The interface between the two is not dense (and there are many defects that allow electrons to move and pass through due to lattice defects in the insulating N2O4 itself, so Electron leakage, ie, leakage current 6, occurred.

However, like the uninvented TPT, an impurity layer 213 doped with an impurity dopant mainly composed of a-5i:H between the a-Si:H semiconductor layer 205 and the insulating layer 204.
When intervening, the energy barrier of the impurity layer 213 causes the insulating layer 204 to flow from the a-3i:H semiconductor layer 205.
It is also difficult for electrons to move to the side, and a-5i:■
Since the semiconductor layer 205 and the impurity layer 213 are basically a-5i:H, which is an interstitial material, there is a defect at the interface between them that is large enough to allow electrons to pass through, just like the a-5 of the conventional TFT.
i:) It is thought that the amount is much smaller than that at the interface where the I semiconductor layer 205 and the insulating layer 204 made of nitride are joined.

For this reason, in the TPT of the present invention, a-Si:H
It is considered that the insulation between the semiconductor layer 205 and the insulating layer 204 is higher than the conventional structure in which the a-3i:)I semiconductor layer 205 and the insulating layer 204 made of nitride are simply bonded. .

On the other hand, the impurity layer 213 is n or n+ type a-5i:)
In the case of a single layer, when a negative gate voltage VG is applied to the gate lid layer 201, an n or n+ type a-3i:8 layer is induced at the interface between the insulating layer 204 and the 3-3i:H semiconductor layer 205. Injection of holes into the insulating layer 204 is suppressed.

That is, in this case, the impurity layer 213 is considered to function as a genuine card blocking layer in place of the above-mentioned electrons.

As described above, the impurity layer 213 formed of p or p+ type a-5i:H or n or n+ type a-5i:H is combined with the insulating layer 204 made of nitride and the a-5i:H semiconductor layer 205. It is thought that this impurity layer 213 functions as a blocking layer for electrons or holes by interposing it between Therefore, if the main objective is to prevent a positive dark value shift due to the application of a positive gate voltage, it is desirable that the impurity layer 213 be formed of a p-type or p-type a-3 isH layer.

FIG. 3 is a schematic diagram showing the configuration of a general device used for manufacturing TPT. Hereinafter, the method for manufacturing TPT of the present invention using the device shown in FIG. 3, and the TPT of the present invention manufactured by this device The results of a comparison of the characteristics between the conventional TPT and the conventional TPT will be explained.

In FIG. 3, reference numeral 100 is a vacuum vessel as a reaction vessel. Inside the reaction vessel 100, a high frequency (radio frequency: RF) electric current B 104 is connected to a matching unit 1.
An RF electrode 101 to which RF power is supplied via 03, and a support base 105 having a built-in heater 111 facing the RF electrode 101 are provided.

Further, a gas introduction part 107 opened to the outside is provided at one end of the reaction vessel 100, and a first gas introduction part 107 is provided at one end of the reaction vessel 100. a second exhaust section 108;
109 are provided respectively. By the way, 102 is R
Place the F electrode 101 into the reaction chamber! It is an insulator for supporting the 5100.

Now, in order to manufacture TPT using such an apparatus, the following processing is generally performed.

First, a substrate 200 such as glass is placed on the support stand 105,
The inside of the reaction vessel 100 is started to be depressurized by the diffusion pump connected to the first exhaust part 108, and at the same time, the heating of the substrate 200 by the heater 111 is started. Then, when the degree of vacuum inside the reaction vessel 100 is reduced to below IX1O-6 Torr, the first
The valve of the exhaust section 108 is closed, and raw material gas whose flow rate is controlled by a mass flow controller (not shown) is introduced from the gas introduction section 107. Along with this, the second exhaust section 1
The valve 09 is opened, and a mechanical booster pump (not shown) connected to the valve is used to adjust the opening degree of the valve so that the pressure inside the reaction vessel 100 reaches a predetermined value. Thereafter, when the pressure inside the reaction vessel 100 stabilizes to a constant level, the RF power source 104 starts to generate 1? By starting to supply RF power to the F electrode 101 and applying a predetermined RF power to the RF electrode 101 while adjusting the RF power using the matching unit 7) 103, the RF power +1xox and the support base 105, more specifically, Plasma is generated between the substrate 200 and the substrate 200 .

The plasma generated in this way causes the gas introduction part 1 to
The raw material gas introduced into the reaction vessel 100 from 07 is thermally decomposed into atoms, and the decomposed atoms, such as Si, are gradually deposited on the substrate 200.

In manufacturing the TPT of the present invention, the insulating layer 204 is formed using a silane-based gas such as monosilane (SiH4) or disilane (Si2H6), and ammonia (NH3), nitrogen (N2), oxygen ( 02
) and other gases containing nitrogen atoms and oxygen rings are used.

Note that the method described above is preferable from the viewpoint that the insulating layer 204 can be formed continuously in the reaction vessel 100, but other methods include aluminum oxide (AI!203), 5fS, which has insulating properties and has a high breakdown voltage. Tantalum oxide (7a205) + boron nitride (BN), oxynitride (SiNxOy), etc. may be used, or a combination of a plurality of these may be stacked and used.

On the other hand, a-3i:l (semiconductor layer 205 or n+ type a
When forming an a-5i:8 layer such as the -3i:H layer 212, a silane-based gas is used as described above, but if necessary, it may contain a group (I) element such as boron (B). By doping a small amount of group (I) elements by mixing diporane (B2H6) gas or the like, an a-Si:8 layer with improved dark resistivity and reduced leakage current may be formed.

Hereinafter, the TP of the present invention actually manufactured using the above-mentioned apparatus will be described.
A conventional TPT for comparison, which is manufactured in exactly the same manner as the TFT of the present invention except that it does not have T and the impurity layer 213, will be described.

In addition, FIG. 2 (al to (Jl) is a schematic diagram showing the manufacturing efficiency of TPT of the present invention.

First, as shown in FIG.
00, a gate electrode layer 201 of Ni--Cr is formed by etching. This gate electrode layer 201 had a gate length of 20 μm steel and a gate width of 300 μm.

Next, the glass substrate 200 on which the gate electrode layer 201 is formed as described above is placed on the support stand 105 inside the reaction vessel 100, and the inside of the reaction vessel 100 is evacuated from the first exhaust part 108 using a diffusion pump (not shown). As the heater 111
The heating of the glass substrate 200 is started by supplying power to the glass substrate 200, and the temperature is adjusted so that the temperature is stabilized at 250°C.

The degree of vacuum inside the reaction vessel 100 is 5 x 10-'T.
When the temperature drops to below orr, the valve of the first exhaust section 108 to which the diffusion pump is connected is closed, and the gas introduction W is closed.
A mass flow controller connected to 107 introduces 20 scyl of monosilane gas and 30 seconds of ammonia gas into the reaction vessel 100, and the mechanical booster pump connected to the exhaust part 109 of the shallow box 2 exhausts the reaction vessel 100. The pulp opening degree of the second exhaust section 109 was adjusted so that the pressure inside the chamber 100 was maintained at 0.15 Torr.

After 5 minutes have passed when the gas flow rate and the internal pressure of the reaction vessel 100 are stabilized as described above, the IIIF power supply 104 is turned on while adjusting the matching unit 103, and the RF electrode 10 is turned on.
1, thereby generating a glow discharge from the RF electrode 101, maintaining the RF power at 30W, and starting power supply to 1.
A SiNx film as an insulating layer 204 was laminated for 2 minutes as shown in FIG.

Next, an impurity layer 213, which is a feature of the present invention, was laminated as shown in FIG. A as the active layer shown in FIG. 2(d) with the process omitted.
-5i: Proceed to the process of forming the H semiconductor layer 205.

Specifically, the impurity layer 213 is formed by turning off the RF power 10 minutes after the above-mentioned insulating layer 204 is formed.
The inside of the reaction vessel 100 is evacuated and its summer emptiness is 5XI
O'' Torr or less. Thereafter, the pulp of the first exhaust section 108 is closed and the raw material gas is introduced into the reaction vessel 100.

In this embodiment, p-type a-3 is used as the impurity layer 213.
i: H impurity layer is used. In this case, boron (B) from Group II Genraku is used as the p-type impurity dopant,
Diporan is used as the raw material gas for this, and a mixed gas of this and monosilane is used at a flow rate ratio of B2H6/5i)
14 = 5Xl0-5, and film formation was performed for 10 minutes.

After the impurity layer 213 is formed as described above, a-5i:
An H semiconductor layer 205 is formed. That is, the flow rate of monosilane gas was set to 30 seconds, and the pressure inside the reaction vessel 100 was set to 0.
, 22 Torr. After 5 minutes, when the gas flow rate and pressure became stable, the RF power source 104 was turned on and the RF power was set to 30 W for 10 minutes to perform a-3i:
An a-Si:H semiconductor layer 205 was formed by laminating eight layers as shown in FIG. 2fdl.

Next, after forming the a-Si:H semiconductor layer 205, the flow rate of monosilane gas was set to 20 sec, the flow rate of ammonia gas was set to 20 sec, and the pressure inside the reaction vessel 100 was set to 0.15 sec.
After 5 minutes, when the gas flow rate and the pressure inside the reaction vessel 100 are stabilized, the RF power source 1 is turned on.
As shown in FIG. 2(e), the S to become the protective layer 211 was heated with the
An iNx layer 2110 was formed.

After that 1? Turn off the F power supply 104 and turn off the gas introduction section 107.
The valve is closed to stop the introduction of the raw material gas, the mechanical booster pump is fully opened to exhaust the inside of the reaction vessel 100 from the second exhaust part 109, and when the temperature of the glass substrate 200 becomes 50° C. or lower, The mechanical booster pump was stopped, the reaction vessel 100 was opened, and the glass substrate 200 was taken out from the reaction vessel 100.

The characteristics of each layer of the thin film layered as described above were as follows.

The insulating layer 204, 5iNxi, has a refractive index of 1.95. The film thickness was 2500 nm, and the optical band gap was 4.2 eV.

P-type a as the impurity layer 213 characterizing the following invention
The dark specific resistance of the -3i:H layer was 1×10 5 Ω·mm, and the activation energy was 0.45 eV. The film thickness was 80 people.

The a-5i:H layer, which is the a-5i:H semiconductor layer 205, has a dark specific resistance of 9×10 9 Ω·1. Activation energy is 0.7
2eV.

The optical band gap was 1.75 eV.

Further, the SiNx layer 2110 that should become the protective layer 211 has a refractive index of 2.05. Ij! The thickness was 1500 nm, and the optical bandgap was 3.5 eV.

As described above, s iN x Ni as the insulating layer 204 and the impurity layer 21 are formed by plasma CVD on the glass substrate 200 on which the gate electrode rrI201 is formed.
3. a-3i: a-Si as H semiconductor layer 205
SiNx layer 2110 to become rH layer and protective layer 211
After each layer is laminated and formed, a source electrode layer 202 and a drain electrode layer 203 are formed by lithography.

Specifically, as shown in FIG.
The part corresponding to 3 was exposed to light as shown in Figure 2 (phantom).

After removing it by development, the surface S is removed using BtIF solution.
As shown in FIG. 2(h), the iNx layer 2110 is formed into a protective layer 2.
Only the portion to be used as No. 11 is left and removed by etching.

After the above processing is completed, the glass substrate 200 is put into the reaction container 100 again and placed on the support stand 105.

Then, while maintaining the temperature of the glass substrate 200 at 100° C., using monosilane and phosphine (PH3) gas as source gases, the n+ type a-5i:Hlti 212 was heated to the second
As shown in Figure 11, the layers were formed. At this time, the monosilane and phosphine gas flow rates were both 20 sec, and the RF
Power is 20W, pressure inside reaction vessel 100 is 0.20To
It was rr.

The n+ type a-5i:0 layer 21 formed in this way
The film properties of No. 2 were as follows: dark specific resistance was 2×10 3 Ω·min, and activation energy was 0.3 eV. Note that the H film thickness was 400 mm. After this, the glass substrate 200 was taken out from the reaction vessel 100, and a second layer of Ni-Cr was deposited to a thickness of 1500 mm by vacuum evaporation.
After depositing as shown in Figure (1) and removing the resist by lift-off etching, a-3i as shown in Figure 2:
HTFT was manufactured.

Experiments conducted on the performance of the TPT of the present invention manufactured as described above and a conventional TPT having the same structure except that it does not have the impurity layer 213 will be described below.

First, conventional TPT does not have an impurity layer 213 between the insulating layer 204 and the a-5i:H semiconductor layer 205 which is the active layer.
When the gate voltage VG and drain voltage VD were set to +20v and drain voltage VD to 5v immediately after manufacture, the dark value voltage VT was +1.5v. Then, with the gate voltage VG as +20V,
Dark value voltage V after DC'gjA movement continues for a period of time
T had shifted to +5.5v.

On the other hand, in the TPT of the present invention, when the dark voltage VT was measured under the same gate voltage VG and drain voltage VD conditions as the conventional TPT described above, it was +1.9V immediately after manufacture, but compared to the conventional TPT. Similarly, if the gate voltage VG is +2
500 hours of DC drive at 0V II! After continuing, it is +4. It was Ov.

In this way, in the conventional TPT, the threshold voltage VT is
．． After 500 hours of DC driving from 5V, it becomes +5.5V and almost 3
．． However, in the TPT of the present invention, the voltage has shifted only about 2.1 times from the initial +1.9V to +4.0V after 500 hours of DC driving.

Next, an example in which an n-type a-3t:H impurity layer is used as the impurity layer 213 will be described.

In this case, the n-type impurity layer 213 is the p-type a-3 described above.
t: Just like when It is used as the impurity layer 213, it is laminated on the surface of the insulating layer 204 in the process shown in FIG.
A <a-3i:H semiconductor layer 205 is laminated as shown in dl.

Now, in order to form an n-type a-3t:H impurity layer as the impurity layer 213, a Group Ⅰ element, in this example, phosphorus (P), is used as the impurity dopant, and the raw material gas is Using phosphine (PI+3) gas, the flow rate ratio with monosilane gas is PH3/5iH4=2X
Film formation was carried out as 10-'.

The electrical characteristics of the n-type a-Si:H impurity layer as the impurity N213 formed in this way are as follows: dark specific resistance is 9.
5 XIO3Ω・Activation energy is 0.45eV
Met. The thickness of the film was set at 50 people.

In the TPT of the present invention using an n-type a-Si:H impurity layer as the impurity layer 213 manufactured in this way,
The gate voltage VG and drain voltage VD are
When the dark voltage VT was measured under the same conditions as in the example in which a p-type a-Si:H impurity layer was used as the PT and impurity layer 213, the initial value immediately after manufacturing was +1.7V, but compared to the conventional p-type a-5 as TPT and impurity layer 213
As in the case of the example using the i:H impurity layer, the voltage was +4.3 V after DC driving was continued for 500 hours with the gate voltage VG being +20 V.

Therefore, this impurity layer 213 is n-type a-3i:)
In the embodiment using an I-impure vA layer, the dark value voltage is approximately 2
．． This means a shift of 5 times, which is almost 3 times the conventional TPT.
．． This is a significant improvement compared to 7 times.

〔effect〕

As described above, in the thin film semiconductor device of the present invention, even after continuous DC driving for a long time, the shift ratio of the dark value voltage is considerably lower than in the conventional device. Therefore, according to the present invention, it is possible to provide a stable and highly reliable thin film semiconductor device with a relatively small shift in dark value voltage.

Incidentally, in the above embodiment, the T
Although PT was formed in layers, it goes without saying that other CVD methods may be used as long as similar semiconductor layers, insulating layers, etc. can be formed in layers.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the structure of a thin film transistor as a thin film semiconductor device of the present invention, Fig. 2 is a schematic diagram showing the manufacturing process by CVD method, and Fig. 3 is a schematic diagram showing the structure of the manufacturing equipment for the same. , FIG. 4 is a schematic diagram showing the structure of a conventional general thin film transistor 200...Substrate 201...
Gate electrode layer 202...source electrode layer 203...
-Drain electrode layer 204...insulating layer 205...a
-St:H semiconductor layer 213...Impurity layer Patent applicant Sumitomo Metal Industries Co., Ltd. Agent Patent attorney Norio Kono V & Wara 4 Figure 11 Figure L3 procedural amendment (voluntary) April 3, 1988

Claims (1)

[Claims] 1. In a thin film semiconductor device having a structure in which a hydrogen-containing amorphous silicon semiconductor layer and an amorphous insulating layer are bonded, at the interface between the semiconductor layer and the insulating layer, 1. A thin film semiconductor device comprising an impurity layer in which a group III or V element of the periodic table is added as an impurity element to a silicon layer. 2. The thin film semiconductor device according to claim 1, wherein the impurity layer has a thickness in a range of 10 Å to 500 Å. 3. The content of the impurity element added to the impurity layer is in the range of 1 x 10^-^4% to 1% in terms of atomic percent when it is a Group III element. The thin film semiconductor device according to item 1. 4. The impurity element is added to the impurity layer in a proportion of 1 atomic percent when it is a Group V element.
The thin film semiconductor device according to claim 1, wherein the concentration is in the range of x10^-^4% to 2%.