JPS6295014A - Waveform equalizer - Google Patents

Abstract

PURPOSE:To suppress the undershoot of a reproducing waveform by constituting the titled equalizer so that a reflection factor is adjusted by a variable resistance element which has been coupled to a termination of the first signal delay element, an asymmetrical voltage signal is generated to a matching end of this first signal delay element, and a voltage signal which has been obtained through this voltage signal and the second signal delay element is weighted, and subtracted and amplified. CONSTITUTION:One end of a delay element 2A is coupled to a signal input terminal IN through a line matching resistance 1, and to the other end of this delay element 2B, a terminal reflection resistance 5 which can set optionally a reflection factor of a signal is connected. Also, to one end of the delay element 2B, a voltage divider 3 used for weighting is connected, and its voltage dividing terminal is connected to a - input terminal of a differential amplifier 4. Moreover, one end of another delay element 2A is coupled to the signal input terminal IN, and to the other end thereof, a terminal matching resistance 6 for eliminating a reflection of a signal is connected, and also it is connected to a + input terminal of the differential amplifier 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a waveform equalizer used in an apparatus for reproducing contents stored in a magnetic storage medium such as a magnetic disk in a high-density variation.

[Conventional technology]

Figure 5 shows, for example, “IEICE Technical Research Report MR76-
13J and is a circuit diagram of a waveform equalizer known as a cosine equalizer conventionally used in VTRs and the like. In the figure, (1) is a line-to-line matching resistor that matches the signal input from the signal input terminal IN with a reflected wave generated at the end of a signal delay element, which will be described later. A signal delay element (hereinafter simply referred to as delay element) % (8
) is a voltage divider that divides the voltage signal appearing at one end of the delay element (2), that is, the matching end, and (4) is a voltage signal divided by the voltage signal at the terminal of the delay element (2) and the voltage signal that has been divided by the voltage divider (3). This is a differential amplifier that amplifies the difference between a voltage signal (hereinafter simply referred to as a signal) and generates it at a signal output terminal 0σT.Next, the operation will be described below with reference to FIG. 6 as well.

Now, as shown in Fig. 6(a), when an isolated waveform signal a reproduced from a recording medium and used as a unit of a report is applied to the fv input terminal IN, Regarding the delay element (2). Assuming that the delay time of the spreading element (2) is T, a signal delayed by 7 hours with respect to the signal a as shown in FIG. 6(b) appears at the end thereof.

- Also, an inter-line j matching resistor (
A composite signal of the signal input through 1) and the signal reflected at the end of the delay element (2) and delayed by 2'r time appears, and this composite signal is applied to the voltage divider (8) for weighting. K, a signal C shown in FIG. 6(C) is obtained. The differential amplifier (4) receives the signal S at the (+) input terminal and the signal C at the (=) input terminal, and amplifies the difference between the two, as shown in FIG. 6(d). Both bases of the isolated reproduced waveform are scraped off to generate a steep waveform signal d at the entire signal output terminal OUT.

In this way, by making the isolated playback waveform sharp and sharp, waveform interference, which can be a problem at high recording densities, can be reduced (
So-called waveform equalization is performed.

[Problem that the invention seeks to solve]

In the conventional waveform equalizer as described above, both bases of the isolated reproduced waveform are equally cut off, so there is no problem in reproduction when the left-right symmetrical isolated reproduced waveform signal is input. However, if the input reproduced waveform is asymmetrical as shown in Figure 7 (Pi), undershoot xf will occur in the output waveform due to the VC shown in Figure 7 (b).
If the input reproduced waveform originally has an undershoot Y, a more emphasized undershoot Z appears as shown in FIG. 4(d).

There is a problem in that the undershoot appearing in the output waveform of the equalizer becomes a pseudo pulse during reproduction by the digital magnetic recording device, leading to the occurrence of errors.

This invention was made in order to solve the problem of the upper tube C, and it is an object of the present invention to provide a waveform equalizer that can reliably suppress the undershoot of the reproduced waveform that leads to the generation of spurious pulses.

[Means for solving problems]

The waveform equalizer according to the present invention includes a first signal delay element connected to a terminal end of a variable resistance element capable of arbitrarily setting a reflectance, and a second signal delay element connected to a terminal end of a variable resistance element capable of arbitrarily setting a reflection factor. a differential amplifier that weights a voltage signal generated at the matching end of the first signal delay element and a voltage signal generated at the terminal end of the second signal delay element, and subtracts and amplifies these weighted signals. It is fully equipped.

A signal delay element having a waveform equalizer according to another aspect of the present invention combined with a variable resistance element capable of setting the reflectance at an arbitrary VC at its terminal end, and having an intermediate tap for signal extraction, and this signal delay element. It is equipped with a differential amplifier which weights the input voltage signal and the voltage signal appearing at the center tap thereof, and subtracts and amplifies these weighted signals.

[Effect]

In the present invention, an asymmetrical voltage signal is generated at the matching end of the first signal delay element by adjusting the area reflectance of the fC variable resistance element coupled to the terminal end of the first 1g delay element, By weighting and subtracting and amplifying this voltage signal and the voltage signal obtained by all the second signal delay elements, undershoot in re-molding can be suppressed.

Further, in another aspect of the present invention, by adjusting the area reflectance of a variable resistance element connected to the terminal end of the signal delay element, the asymmetrical voltage signal appearing at the center tap of the signal delay element and the input The undershoot of the reproduced waveform is suppressed by weighting and subtracting and amplifying the signal.

〔Example〕

FIG. 1 shows a circuit □□□ showing one embodiment of the present invention.

In the same figure, one end of the delay element (2A) is connected to the signal input terminal IN through the line matching resistor (1), and the other end of the delay element (2B) is connected to the signal reflection factor. A terminating reflective resistor (5) that can be set is connected. Further, a voltage divider (3) used for weighting is connected to one end of the delay element (2B), and its voltage dividing terminal is connected to the (-) input terminal of the differential amplifier (4). Furthermore, one end of another delay element (2A) is coupled to the signal input terminal INK, and a termination matching resistor (O) for eliminating signal reflection is connected to the other end. ! vessel(
4) VC connected to the (→input terminal) The operation of the embodiment configured as described above will be explained below with reference to FIG.

First, the 4 delay time of delay element (2A) is T□, delay element 2
As the delay time sound T2 of B, the falling part of the waveform undershoots as shown in Figure 2 (a) and the t signal e
is added to the signal input terminal INi'i, the signal f with the same waveform but delayed by T1 time becomes a differential signal f as shown in FIG. 2(b).
It is added to the (+) input terminal of the lucky device (4). On the other hand, when the f signal e is applied to the delay element (2B) via the line matching resistor (1), the reflected signal is delayed by 2T2 time with a magnitude determined by the value of the terminal reflective resistor (6). A signal having a rain-permeable part with respect to the signal e appears at the matching end of the delay element (2B). This signal voltage divider (8)
A signal g shown in FIG. 2(C) is applied to the (-) input terminal of the differential amplifier (4). Here, the delay time T + T2Th of the delay elements (2A) and (2B) is determined so that the suitable part of the signal g overlaps with the undershoot part of the signal f and its size is approximately equal to the size of the undershoot. At the same time, the terminal reflection resistance (5
) and the voltage divider tJl'i, as shown in FIG. 2(d), the broadening of the base of the rising portion of the reproduced waveform is removed, and the undershoe of the rising 9 portion of the reproduced waveform is corrected. You can get more.

Next, FIG. 3 is a circuit diagram of an embodiment according to another invention of the present invention, and whereas the above-mentioned embodiment uses two delay elements, here a delay element with a center tap ( a) It's all around. In the same figure, a delay element with an intermediate tap (
a) One end is the line matching resistor (1) All valves are connected to the signal input terminal I
A terminating reflective resistor (5) is connected to the NVC and the other end, allowing the reflectance of the signal to be arbitrarily set. The intermediate tap of the delay element (A) is connected to the (+) input terminal of the differential amplifier (4). Further, a voltage divider (8) is connected to the signal input terminal IN, and its voltage dividing terminal is connected to the (-) input terminal of the differential amplifier (4).

The operation of this embodiment will be explained below.

First, as shown in Fig. 4 (1), an asymmetrical signal e whose falling part of the waveform undershoots is output to the signal input terminal I.
When added to N, a signal J having a delay amount of zero and weighted by L to the voltage divider (3) is applied to the (-) input terminal of the differential amplifier (4).

On the other hand, if delay element (7) tri is delayed by 73 hours on the signal input side and delayed by 74 hours on the signal reflection side as seen from the intermediate tap, the signal delayed by T3 hours with respect to signal e and the terminal reflection resistor ( 5), a composite signal with a signal further delayed by 2T time appears at this intermediate tap, and the signal k shown in FIG.
) applied to the input terminal. Thus, from signal k to signal J
The signal shown in FIG. 4(d), in which the broadening of the base of the rising part of the reproduced waveform is removed and the undershoot of the falling part of the reproduced waveform is corrected, is obtained by subtracting and amplifying the signal shown in FIG. 4(d). 4) is output.

Although resistors were used for matching and voltage division in the above-mentioned embodiments, for example, even if the resistors include inductance, if the entire signal applied to the differential amplifier is delayed relative to the total, the result will be almost the same as that described above. Waveform equalization is possible, and in this sense, not only pure resistance but also what is widely called an @resistance element may be used.

〔Effect of the invention〕

According to the present invention, the reproduction waveform can be changed by simply selecting the delay time of the delay element and the value f of the variable resistance element connected to the signal reflection end of the delay element according to the reproduction waveform of magnetic recording. Since the undershoot can be corrected, the generation of spurious pulses can be reliably prevented, which has the effect of widening the range of application of the waveform equalizer itself.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2(a) -
(d) is a waveform diagram for explaining the operation of the same embodiment;
The figure shows a circuit diagram of an embodiment according to another invention, FIG. 4(a) to (
d) is a waveform diagram for explaining the operation of the same embodiment, FIG. 5 is a circuit diagram of a conventional waveform equalizer, FIGS. ) is the dynamic f'1 of this waveform equalizer
1. FIG. 2 is a waveform diagram for explaining. (1)...Line matching resistor (2A), (2B)...Signal delay element (8), Participant voltage regulator (4), Differential amplifier (5)
・Terminal reflection resistance (6) ・Terminal matching resistance (A) ・・
Delay element with intermediate tap Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) One end is coupled to the signal input end via a resistive element,
A first signal delay element has one end connected to a variable resistance element whose reflectance can be set arbitrarily, and a first signal delay element whose one end is coupled to the signal input terminal and whose other end is connected to a resistance element which can eliminate reflection. weighting a voltage signal appearing at one end of the first signal delay element and a voltage signal appearing at the other end of the second signal delay element when a voltage signal is applied to the signal input terminal; 1. A waveform equalizer comprising a voltage divider that performs the following: and a differential amplifier that subtracts and amplifies these weighted voltage signals. (2) one end is coupled to the signal input end via a resistive element,
A signal delay element with an intermediate tap to which a variable resistance element whose reflectance can be arbitrarily set is connected to the other end, and a voltage signal applied to the signal input terminal and a voltage signal generated at the intermediate tap of the delay resistance element. 1. A waveform equalizer comprising: a voltage divider that weights voltage signals; and a differential amplifier that subtracts and amplifies these weighted voltage signals.