JPS6293730A - Central processor - Google Patents

Abstract

PURPOSE:To simplify many macro-instructions, and to improve the processing speed by storing a bit field contained in a storage device, into a register by reversing its bit sequence. CONSTITUTION:A data of 32 bits containing a bit field of 16 bits, which has been read out of a storage device 1 is read in a data register 3, and inputted to a shift device 4. By the shift device 4, the data of 32 bits is shifted to the left by the number of bits shown by a bit position, the bit field becomes upper 16 bits of the data, and as for this shifted data, only the upper 16 bits are inputted to a shift register 5 through a data bus 12. This state is an output of upper 16 bits of the shift device 4, and each bit of the bit field is represented as (a), (b),...(o), and (p) from the upper bits. As for the data selector 5, a select signal 13 becomes a state of '1' by a control device 7, therefore, it is outputted in a state that a bit sequence of an input has been reversed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a central processing unit, and in particular to a central processing unit that processes a bit-length bit of l word length contained in data stored in a storage device in order to simplify calculations. - It relates to a central processing unit equipped with a bit field manipulation device that changes the order of bits.

〔overview〕

The present invention provides a central processing unit equipped with a bit field manipulation device that changes the bit order of a one-word length bit field included in data stored in a storage device. The processing speed when reversing the bit order is increased by including means for reading out data containing a 1-word length bit field, reversing the bit order of the 1-word length bit field, and storing it. It is.

[Conventional technology]

Conventionally, this type of bit field manipulation device simply reads data from a storage device and stores the bit field data in a register, but does not reverse the bit order.

[Problem that the invention seeks to solve]

The conventional bit field manipulation device described above is as follows. !
Since the bit field is simply read from the device and stored in the register, reversing the bit order of the bit field requires many macro instructions and has the disadvantage of slow processing speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a central processing unit equipped with a bit field manipulation device that increases the processing speed when reversing the bit order by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a central processing unit equipped with a bit field manipulation device for changing the order of one word length bit fields of data stored in a t9 device, wherein the storage device stores one word length bit fields. The bit field manipulation device stores a macro instruction for reversing the bit order of the one word length bit field, and an address of the bit field specified by this macro instruction. and the bit position thereof; a data register storing two-word length data including the bit field read from the storage device; and a data register storing the data stored in the data register at the bit position. a data selector connected to reverse the bit order of the bit field left-justified by this shift device; The method is characterized in that it includes a register that stores the inverted bit field, and a control device that controls execution of the macro instruction.

C operation] The present invention stores 2-word length data including a 1-word length bit field in a storage device, reads and stores the data in a data register according to a macro instruction stored in an instruction storage device, and sequentially shifts the data to a data register. sent to. The shift device shifts the data to the left by the number of hits indicated by the bit position (indicates from which bit of the address the bit field starts) stored in the instruction storage device in advance, and sets the bit field to the upper bit. do. The bit order of the bit field shifted to the higher order bits is reversed using a data selector. Then, this bit field with the bit order reversed is stored in a register. In this way, it is possible to reverse the bit order of the one word length bit field stored in the memory H1.

In other words, the necessary macro instructions are simplified and the processing speed is improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. 1 is a storage device which stores data of 32 bits in length of 2 words including a bit field of 16 bits in length of 1 word. 2 is an instruction storage device that stores macro instructions, bit field addresses, and bit positions. 3 is 3
A 2-bit data register stores 32-bit data including a 16-bit field read from the storage device 1. 4 is data by the shift device and register 3
Shift the data to the left by the number of hits indicated by the bit position, and set the bit field in the upper 16 bits. 5 is a 16-bit data selector connected so that the bit order of the bit field shifted to the upper 16 bits/nodes by the shift device 4 is reversed. , 6 are registers that store bit fields whose bit order has been reversed by the data selector 5. 7 is a control device which sends control signals to each part of 1 to 6 as necessary. Reference numeral 10 denotes a 32-bit external lotus for storing 32 bits of data including bit fields sequentially outputted from the storage device 1 into the data register 3. A 32-bit data bus 11 inputs the data of the data register 3 to the shift device 4. 12 is a 32-pin data bus for storing the output of the shift device 4 into the register 6 through the data selector 5. 13 is a select signal of the data selector 5.

The feature of the present invention is that, in FIG. 1, an instruction storage device 2, a data register 3, a shift device 4, a data selector 5, a shift register 6, and a control device 7 are provided, and a bit field of one word length is stored in the storage device 1. It is designed to be able to store 2-word length data.

Next, the operation of this embodiment will be explained by explaining the data including bit fields in the storage device 1 in FIG. 2, by explaining the output of the shift device 4 in FIG. This will be explained using a function explanatory diagram. 3 containing the 16-bit bit field shown in FIG. 2 read from the storage device 1.
The data of 2 pins 1- is read into the data register 3 through the external path 10. This 32-bit data is input to the shift device 4 through the data bus 11. The 32-bit data is shifted to the left by the shift device 4 by the number of bits indicated by the bit position, so that B in FIG. 2, that is, the bit field, becomes the upper 16 bins of the data.

Only the upper 16 bits, that is, the bit field, of this shifted data are input to the data selector 5 through the data bus 12. This state is the shift device 4 in Fig. 3.
The output of the upper 16 bits of the bit field is a, b from the upper order.

It is expressed as C1----1o3p. The data selector 5 has the select signal 13 set to “1” by the control device 7.
, the input bit order is reversed and output. This means that the select signal 13 in FIG.
1", the output from the data selector 5 is stored in the register 6 with the bit order of the bit field reversed.

〔Effect of the invention〕

As explained above, the present invention reverses the bit order of a bit field in a storage device and stores it in a register, thereby simplifying the many macro instructions conventionally required to reverse the bit order. This has the effect of significantly increasing processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is an explanatory diagram of data including bit fields. FIG. 3 is an explanatory diagram of the upper 16 bits of the output of the shift device in FIG. 1. FIG. 4 is a functional explanatory diagram of the data selector shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Storage device, 2... Instruction storage device, 3... Data register, 4... Shift device, 5... Data selector, 6... Register, 7... Control device, 10・
...External bus, 11.12...Data bus, 13...
・Select signal, A...Bit position, B...
bit field.

Claims (1)

[Claims] (1) In a central processing unit equipped with a bit field manipulation device that changes the bit order of a 1-word length bit field of data stored in a storage device, the storage device includes 2 bit fields that have a 1-word length.
The bit field manipulation device is configured to store word length data, and includes a macro instruction for reversing the bit order of the one word length bit field, an address of the bit field specified by this macro instruction, an instruction storage device that stores the bit position; a data register that stores 2-word length data including the bit field read from the storage device; a data selector connected to reverse the bit order of the bit field left-justified by the shift device; and a data selector connected to reverse the bit order of the bit field left-justified by the shift device. A central processing unit comprising: a register that stores the bit field that has been read; and a control device that controls execution of the macro instruction.