JPS6292042A - Memory device - Google Patents

Abstract

PURPOSE:To easily diagnose the instruction retry function of a system controller by producing selectively the fixed and intermittent errors based on the output signal of an intermittent error setting register. CONSTITUTION:When a control signal 11 is sent to a control circuit 4 from a system controller, the circuit 4 gives an instruction for a diagnosis writing action. The diagnosis data 7 and 9 are sent to an intermittent error setting register 1 and a pseudo trouble register 2 later than the signal 11 by a clock. The logic 1 is set to both registers 1 and 2. The output signals 8 and 10 of registers 1 and 2 and an action instructing signal 12 are supplied to an AND gate 3. Thus the AND of said signals sets a pseudo trouble resetting signal 13 at logic 1 and both registers 1 and 2 are reset. As a result, it seems that not only a fixed error but an intermittent error are produced to the system controller.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a storage device having a maintenance/diagnosis function.

In particular, it concerns the generation method of pseudo-faults.

[Conventional technology]

Conventionally, when a system control device executes write and read commands to a storage device with a pseudo failure set in a diagnostic register by a maintenance diagnostic function, an error always occurs. That is, it becomes a fixed error.

[Problem that the invention seeks to solve]

As mentioned above, simply setting a pseudo failure in one diagnostic register will make the error appear fixed to the system control unit, and the system control unit will use the instruction retry function to
When the address where the error occurred is accessed again, the address area that was shear accessed in error is separated. Therefore, although it is possible to diagnose a fixed error in the command try function, there is a problem in that it is not possible to diagnose a successful retry that will not result in an error when accessed again.

[Means for solving problems]

The storage device according to the present invention executes write and read operations in response to write and read commands from the system control device, and also has a maintenance diagnosis function. A pseudo-fault register that sets a pseudo-fault according to the function, an intermittent error set register that sets whether the error is an intermittent error or a fixed error, an output signal of the pseudo-fault register, an output signal of the intermittent error set register, and the system controller. and a write or read operation instruction signal, and a reset means for resetting the pseudo-fault register using the AND signal, and selectively generating an error detection error based on the output signal of the pseudo-fault register. It is characterized by allowing

〔Example〕

Next, the present invention will be explained with reference to examples.

Referring to FIGS. 1 and 2, a control signal such as a request (this request is sent in the order of diagnostic write operation 2, normal write or read operation, and normal write or read operation) from the system control device (not shown) 11 is sent to the control circuit 4, the control circuit 4 instructs a diagnostic writing operation. One clock later than this control signal (request) 11, diagnostic data 7 and 9 are sent to the intermittent error set register 1 and pseudo-fault register 2, respectively. Set.

A control signal 11 such as a request for a normal write or read operation is sent to the control circuit 4 at the next clock after the request for a diagnostic write operation, and the control circuit 4 instructs the normal write or read operation. In the case of a normal write or read operation, the operation instruction signal 12 becomes logic "1". Therefore, the error detection circuit 5 operates.

An error signal 15 is generated which is sent via an error register 6 to the system controller. On the other hand, when there are two intermittent errors, the output signal of register 18. Output signal 10 of pseudo fault register 2. and an operation instruction signal 12 are input to the ANDR port 3.

Moreover, these output signals 8, 10 . and operation instruction signal 12
is a logic "1". Therefore, the logical product of these output signals 8.10 and the operation instruction signal 12 causes the pseudo fault NIJ set signal 13 to become a logic "1". Pseudo fault reset signal 1
3 becomes logic "1", 1 intermittent error set register 1
And the pseudo fault register 2 is reset.

Next, when a control signal 11 such as a normal write or read operation request with a delay of one clock is sent to the control circuit 4, the control circuit 4 instructs a normal write or read operation, and the operation instruction signal 12 becomes logic "1". However, since the pseudo-fault register 2 is reset to the logic "0", the error detection circuit 5 does not operate and no error occurs.

Due to the above operation, it appears that an intermittent error has occurred in the system control device.

Next, the output of the intermittent error set register 1 is set to logic "ON", and the pseudo fault register 2 is set to logic "1". By the way, as mentioned above, pseudo-failure reset.

Since the output signal 13 is at logic "0", the error detection circuit 5 operates and sends an error signal 16 to the system controller every time a normal write or read command is received. Therefore, it appears to the system controller that a fixed error has occurred.

〔Effect of the invention〕

As explained above, in the storage device according to the present invention.

It is equipped with an intermittent error set register for setting whether a pseudo fault is a fixed error or an intermittent error, and a pseudo fault register for setting a pseudo fault, and output signals of these intermittent error set and pseudo fault register, and a system control device. The pseudo-fault register is reset based on the AND with the operation instruction signal from be able to. Therefore, there is an effect that diagnosis of the command retry function of the system control device can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention, and FIG. 2 is a timing chart of each signal in FIG. 1. 1... Intermittent error set register, 2... Pseudo fault register, 3... AND gate, 4... Control circuit,
5...Error detection circuit, 6...Error register, 7
, 9... Diagnostic controller, 8... Intermittent error set signal, 10... Pseudo failure signal, 11... Control signal, 12
...Operation instruction signal, 13...Pseudo failure reset signal, 14...Internal error signal, 15.16...Error signal.

Claims (1)

[Claims] 1. In a storage device that executes write and read operations in response to write and read commands from a system control device and is equipped with a maintenance diagnosis function and is capable of setting pseudo-faults, the maintenance diagnosis function sets pseudo-faults. an intermittent error set register for setting whether the error is an intermittent error or a fixed error;
performing a logical product of the output signal of the pseudo-fault register, the output signal of the intermittent error set register, and a write or read operation instruction signal from the system control device;
a reset means for resetting the pseudo-fault register by the AND signal; and an error detection means for detecting an error based on the output signal of the pseudo-fault register; , a storage device characterized by selectively generating fixed errors and intermittent errors.