JPS6286909A - Variable gain amplifier - Google Patents

Abstract

PURPOSE:To avoid saturation of a transistor by raising base input DC voltage of a differential couple transistor by voltage drop produced in an emitter resistor. CONSTITUTION:Collector terminals of transistors 5, 6 are connected to collector terminals of transistors 7, 8. By raising base input DC voltage of transistors 5, 6 of differential couple by voltage drop produced in emitter resistors 11, 12 by power sources 15, 16, for level shifting saturation of a transistor 2 is evaded. That is, input DC voltage to transistors 5, 6 of low gain side differential couple by at least voltage drop in emitter resistors 11, 12 is raised by power sources 15, 16 for level shifting and inputted, and collector terminals of transistors 5, 6 are connected directly to load resistances 9, 10 without using cascode transistors 7, 8 and output signals are obtained therefrom. Thus, the saturation of the transistor 2 is evades.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a variable gain amplifier, and more particularly to a variable gain amplifier that prevents saturation of transistors, which are five circuit elements, at low power supply voltages. be.

[Background of the invention]

Wideband, high gain, and low noise as a variable gain amplifier for receiving circuits used in optical transmission modules, etc.

Since there are many conflicting requirements such as wide dynamic range, and circuit stability makes it difficult to use a feedback amplifier, a cascode type differential amplifier is used. However, when a variable gain amplifier (hereinafter referred to as an AGC amplifier) is constructed using this circuit configuration, a problem arises in which transistors, which are circuit elements, become saturated. Therefore, at present, the power supply voltage is set high to avoid transistor saturation. Specifically, in order to avoid the Miller effect that causes band limitations, cascode amplifiers have been used in which a transistor is inserted between the collector of an amplification transistor and a load resistor. This cascode amplifier is differentially amplified,
If the cascode amplifiers with different gains are configured so that the gain is variable, a circuit like that shown in FIG. 3 is obtained. The circuit shown in FIG. 5 is already known from Japanese Patent Publication No. 59-20201, and its structure and operation will be explained below.

In Fig. 6, A is an AGC control signal source, B is an amplified signal source, 1 to 8 are NPN type transistors, and transistors 1, 2.3, 4.5, 6.7, and 8 are differential They are set up as a pair. 9 to 12 are load resistors, and output signals are obtained from the load resistors 9 and 1o. Reference numeral 16 indicates a constant current source, and reference numeral 14 indicates a cascode power source, which are connected as shown in the figure.

In Fig. 3, if transistors 3 and 4 are used as high-gain amplification transistors and transistor 5.6 is used as a low-gain amplification transistor, the emitter terminal of transistor 5.6 has a current feedback tank. Emitter resistors 11.12 are connected and functional. When designing a high-gain amplifier using cascode transistors 7.8, the power supply voltage was not high enough.
If the potential difference between the emitter of transistor 6.4 and the emitter of transistor 1.2 has a value close to the voltage between the base and emitter of the transistor, this variable gain amplifier will be used on the low gain side. A constant current source 13 is connected to transistor 2 of the differential pair transistors 1.2.
There was a problem in that when the transistor 2 was controlled to flow all of the current, saturation occurred in the transistor 2 due to a voltage drop across the emitter resistors 11 and 12.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable gain amplifier using a cascode amplifier, which avoids the problem of transistor saturation in the prior art described above, and also without increasing the power supply voltage.

[Summary of the invention]

The features of the present invention are as follows. In other words, the cause of the saturation that occurs in the conventional circuit described above is that even the differential amplifier, which can achieve a wide band on the high gain side if used at a low gain, is in a cascode connection state. For example, the input DC voltage to the high gain amplifier is constant. The present invention focuses on this point and avoids the saturation of the transistor 2 by increasing the base DC voltage of the differential pair transistor 5.6 by the voltage drop occurring in the emitter resistor 11.12 of FIG. The point is that it is configured like this.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 2. FIG. 1 is a circuit configuration diagram of a specific AGC amplifier, and components having the same reference numerals as those in FIG. 3 have the same functions.

Reference numeral 15.16 indicates a level shifting voltage source connected to the base terminal of the transistor 5.6. The collector terminal of transistor 5.6 is connected to the collector terminal of transistor 7.8. In FIG. 1, the voltage drop across the emitter resistor 11.12 is reduced by the level shifting power supply 15.16 of the differential pair of transistors 5.1.
This configuration avoids saturation of the transistor 2 by increasing the base input DC voltage of the transistor 6. To explain in more detail, the input DC voltage to the transistors 5 and 6 of the low-gain differential pair is controlled by at least the emitter resistor 11.12.
The level shift power supply 15.16 increases υ by the voltage drop at , and inputs the voltage, and connects the collector terminal of the transistor 5.6 directly to the load resistor 9.10 without using the cascode transistor 7.8. , from which an output signal is obtained. This avoids saturation of transistor 2.

Although FIG. 1 has shown and explained the invention in principle, FIG. 2 is intended to explain it in more detail. In FIG. 2, the same reference numerals as in FIGS. 1 and 5 have the same functions. In FIG. 2, transistors 17 and 18 are inserted into the base terminals of transistors 3 and 4, respectively, the base terminals of which are connected to the amplified signal source B, and the collector terminals of which are connected to the DC power source. That is, the same configuration has an emitter follower transistor 17.1 for level shifting.
The collectors of differential pair transistors 5 and 6, whose gains are suppressed by emitter resistors 11 and 12, are directly connected to load resistors 9 and 10 without going through a cascode transistor.

Hence the base of transistor 17.18.

Saturation of the transistor 2 due to the voltage drop caused by the emitter resistor 11.12 is avoided by the emitter voltage.For example, if the cascode voltage (power supply 14) in FIG. 3 described above is 4V, the gain control voltage, that is, the transistor 1. If the base voltage of the transistor 2 is 2V and the voltage between the base and emitter of the transistor is 0.9V with respect to the current determined by the constant current source 13, when the circuit is controlled to the low gain side, The collector voltage of the transistor 5.6 of the low gain amplifier is 6.1V.

At this time, in order for the transistor 5.6 not to be saturated,
The base voltage of this transistor also needs to be around 6.1V. The voltage margin of emitter resistance 11°12 is 0
．． The conventional circuit had a problem in that the gain control range was very narrow at 2V.

On the other hand, according to the circuit of FIG. 2 which is an embodiment of the present invention, the cascode voltage (power supply 19) is
When 4r, transistors 5, 6, 17,
The input DC voltage to 18 must also be around 4V or less, and at this time, the emitter voltage of transistor 5.6 is 5.1V.
It becomes V.

Therefore, the voltage drop margin of the emitter resistors 11 and 12 is up to 1.1 V, and there is an extra gain variable width.

〔Effect of the invention〕

As is clear from the embodiments described above, according to the present invention, the high gain amplifier circuit pair is connected in cascode without increasing the power supply voltage, the band is extended, and the emitter in the low gain amplifier circuit pair is connected in cascode. This has the effect of avoiding saturation of the transistor due to voltage drop across the resistor.

[Brief explanation of drawings]

FIG. 1 is a basic circuit configuration diagram for explaining the present invention,
FIG. 2 is a circuit diagram showing an example of a specific configuration of the present invention, and FIG. 3 is a configuration diagram of a conventionally used cascode variable gain amplifier circuit.

Claims (1)

[Claims] a first transistor whose base is supplied with a first input signal; a second transistor which is differentially connected to the first transistor; a collector output of the first transistor is supplied to its emitter; a third transistor whose base is supplied with the second input signal; a fourth transistor which is differentially connected to the third transistor; a collector output of the second transistor is supplied to the emitter; a fifth transistor whose base is connected to the second input signal via a level shifter; and a fifth transistor which is differentially connected to the fifth transistor and has a level shifter similar to that provided between the third and fifth transistors. a sixth transistor which is connected to the fourth transistor, the collector output of the third transistor is supplied to the emitter, and a seventh transistor to which a base bias voltage is supplied, and the collector output of the fourth transistor; is supplied to the emitter of the eighth transistor, the base of which is connected to the base of the seventh transistor; the collector of the seventh transistor is connected to the collector of the fifth transistor; and a load resistor connected to the collector of the transistor and the collector of the sixth transistor, and connected to the collector of at least one of the seventh transistor and the eighth transistor, the load resistor A variable gain amplifier characterized in that it is configured to obtain an output signal from.