JPS6285444A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS6285444A JPS6285444A JP22520185A JP22520185A JPS6285444A JP S6285444 A JPS6285444 A JP S6285444A JP 22520185 A JP22520185 A JP 22520185A JP 22520185 A JP22520185 A JP 22520185A JP S6285444 A JPS6285444 A JP S6285444A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- manufacturing
- semiconductor device
- insulating layer
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000005530 etching Methods 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 239000005360 phosphosilicate glass Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003189 isokinetic effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- UNRFQJSWBQGLDR-UHFFFAOYSA-N methane trihydrofluoride Chemical compound C.F.F.F UNRFQJSWBQGLDR-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009331 sowing Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
等方性エツチングによるサイドエツチングが可能で、か
つ絶縁層の異方性エツチングに対するマスク性を有する
マスク層を用いてコンタクト孔を形成し、微細な二Ｊン
タクト孔の段差を緩和し、配線層の断線を防止する製造
方法を提供する。[Detailed Description of the Invention] [Summary] A contact hole is formed using a mask layer that allows side etching by isotropic etching and has masking properties against anisotropic etching of an insulating layer, thereby forming a fine two-J contact. Provided is a manufacturing method that reduces the level difference in holes and prevents disconnections in wiring layers.
本発明は半導体装置の製造方法に係り、特に段差被覆を
改善できるコンタクト孔の形成方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact hole that can improve step coverage.
半導体装置の製造においては、絶縁層を介して配線層と
半導体基板、あるいは半導体基板上に形成された導電層
等の下地との間に電気的接続を行う場合、絶縁層にコン
タクト孔を開けて露出した下地の上に配線層を形成し、
両者を接触させている。In the manufacture of semiconductor devices, when electrical connections are made between a wiring layer and a semiconductor substrate or a base such as a conductive layer formed on a semiconductor substrate via an insulating layer, contact holes are formed in the insulating layer. A wiring layer is formed on the exposed base,
It brings the two into contact.
この場合、デバイスの微細化にともない、コンタクト孔
は小さく、深くなり、配線層の被覆が困難になるため、
その断面形状を工夫して配線層の段差被覆を改善する方
法が種々試みられている。In this case, as devices become smaller, contact holes become smaller and deeper, making it difficult to cover the wiring layer.
Various methods have been attempted to improve the step coverage of the wiring layer by devising its cross-sectional shape.
微細なコンタクト孔の従来の形成方法は、レジストマス
クを用いて、リアクティフ゛イオンコニツチング（ＲＩ
Ｂり法による垂直方向に優勢な異性性エツチングで行っ
ていた。The conventional method for forming fine contact holes is to perform reactive ion conniting (RI) using a resist mask.
This was done using isomeric etching with a predominance in the vertical direction using the B-etching method.
このとき、メルト等により絶縁層に開けられたコンタク
ト了りの肩をなだらかににしても、二Ｉンタクト孔が微
細なため配線層の被覆は非常に不利なものである。At this time, even if the shoulder at the end of the contact made in the insulating layer is made smooth by melting or the like, it is very disadvantageous to cover the wiring layer because the contact hole is minute.
さらに、改良された方法として、レジストマスクを用い
て等方性エツチングと異性性エツチングを用いてコンタ
クト孔の肩を面とりする方法が行われている。Furthermore, as an improved method, a method of chamfering the shoulders of contact holes using isotropic etching and isotropic etching using a resist mask has been used.
第３図（１１、（２）は従来例による改良されたコンタ
クト孔形成方法である。FIG. 3 (11, (2)) shows an improved contact hole forming method according to the conventional example.
第３図（１）において、下地１の上に絶縁層２を被着し
、その」−にレジスト４を塗布しコンタクト孔形成部を
開［−１する。In FIG. 3(1), an insulating layer 2 is deposited on a base 1, and a resist 4 is applied thereto to open a contact hole forming area.
つぎに、等方性エツチングにより、レジスト４の下まで
絶縁層２をアンダーカットし、続いて異性性エツチング
により、絶縁層２を開「１して下地１を露出さ・口、コ
ンタクト孔を形成する。Next, the insulating layer 2 is undercut to the bottom of the resist 4 by isotropic etching, and then the insulating layer 2 is opened by isotropic etching to expose the base 1 and form a contact hole. do.
第３図（２）において、レジストを除去後、コンタクト
孔を覆って配線層５、カバー絶縁層６を形成する。In FIG. 3(2), after removing the resist, a wiring layer 5 and a cover insulating layer 6 are formed to cover the contact hole.
この場合において４）、図のＡ、８点の個所が滑らかで
ないため、配線層の被覆がよくない。In this case, 4) The 8 points A in the figure are not smooth, so the wiring layer coverage is not good.
従来のコンタクト孔の形成方法では、配線層の段差被覆
が悪く、断線の危険がある。In the conventional method of forming contact holes, the step coverage of the wiring layer is poor and there is a risk of disconnection.
一１二記問題点の解決は、下地（１）上に、絶縁層（２
）と、マスク層（３）と、レジスト（４）とを順次被着
し、該しシスト（４）の：ノンタクト孔形成領域に開１
」部を形成し、等方性エツチングにより、該マスク層（
３）を該開口部の面積より大きく除去し、異方性エツチ
ングにより、該絶縁層（２）を略該開口部の面積で厚さ
方向に厚さの途中までを除去し、レジスＩ−（４）を除
去して、該マスク層（３）をマスクにした異方性エツチ
ングにより、該絶縁層（２）を除去して核上ｊ１！！（
１１を露出させる工程を含む本発明による半導体装置の
製造方法、および
下地（１）上に、絶縁層（２）と、マスク層（３）と、
レジスト（４）とを順次被着し、該レジスト（４）の二
ｌンタクト孔形成領域に開口部を形成し、等力性上ソチ
ングにより、該マスク層（３）を該開口部の面積より大
きく除去し、かつ該絶縁層（２）の一部を除去し、異方
性エツチングにより、該絶縁層（２）を除去して該下地
ｆ１１を露出させる工程を含む本発明による半導体装置
の製造方法により達成される。The solution to the problem No. 112 is to add an insulating layer (2) on the base (1).
), a mask layer (3), and a resist (4) are sequentially deposited, and an opening 1 is formed in the non-tact hole forming area of the cyst (4).
” portion, and isotropically etched the mask layer (
3) is removed to be larger than the area of the opening, and by anisotropic etching, the insulating layer (2) is removed up to the middle of the thickness in the thickness direction approximately in the area of the opening, and the resist I-( 4), and by anisotropic etching using the mask layer (3) as a mask, the insulating layer (2) is removed and j1! ! (
11, and an insulating layer (2), a mask layer (3) on a base (1),
A resist (4) is sequentially deposited, an opening is formed in the contact hole formation region of the resist (4), and the mask layer (3) is reduced in area by isokinetic sowing. Manufacturing a semiconductor device according to the present invention, including a step of removing a large portion of the insulating layer (2), removing a part of the insulating layer (2), and removing the insulating layer (2) to expose the base f11 by anisotropic etching. This is accomplished by a method.
前記下地（１）が半導体基板、あるいは半導体基板上に
被着された導電層である、
前記マスク層（３）が多結晶珪素層、あるいは窒化珪素
層である、
前記絶縁層（２）が燐珪酸ガラス層、あるいは二酸化珪
素層である
場合は特に本発明の効果が顕著である。The base (1) is a semiconductor substrate or a conductive layer deposited on the semiconductor substrate. The mask layer (3) is a polycrystalline silicon layer or a silicon nitride layer. The insulating layer (2) is a phosphorus layer. The effects of the present invention are particularly remarkable when the layer is a silicate glass layer or a silicon dioxide layer.
本発明は、レジストをマスクにした等方性エツチングに
よるサイドエツチングが可能で、かつ絶縁層の異方性エ
ツチングに対するマスク性を有するマスク層を用いて、
まずマスク層を等方性エツチングによりサイドエツチン
グしてコンタクト孔よりやや大きい孔を開け、このマス
ク層を利用して肩のだれた断面形状を有するコンタクト
孔を形成し、コンタクト孔の段差を緩和し、配線層の断
線を防止するものである。The present invention enables side etching by isotropic etching using a resist as a mask, and uses a mask layer that has masking properties against anisotropic etching of an insulating layer.
First, the mask layer is side-etched using isotropic etching to form a hole slightly larger than the contact hole, and this mask layer is used to form a contact hole with a sagging cross-sectional shape to reduce the level difference in the contact hole. , to prevent disconnection of the wiring layer.
第１図＋１１〜（６）は第１の本発明によるコンタクト
孔の形成方法を工程順に説明する断面図である。FIGS. 11-16 are cross-sectional views illustrating the method of forming a contact hole according to the first aspect of the present invention in the order of steps.
第１図（１）において、１は下地で、例えば珪素（Ｓｉ
）％板で、この」−に化学気相成長（ＣＶｌｌ）法によ
り、絶縁層として厚“さｌｔｔｍの燐濃度の大きい燐珪
酸ガラス（＋１−ＰＳＧ）層２、マスク層として厚さ２
０００人の多結晶珪素（ポリＳｉ）層３を順次被着する
。In FIG. 1 (1), 1 is the base material, for example silicon (Si).
)% plate, a layer 2 of phosphosilicate glass (+1-PSG) with a high phosphorus concentration of 2" thick as an insulating layer and a layer 2 of phosphorus silicate glass (+1-PSG) with a thickness 2" as a mask layer is formed on this "-" by chemical vapor deposition (CVll) method as an insulating layer.
000 polycrystalline silicon (poly-Si) layers 3 are deposited one after the other.
つき゛に、その−にに厚さ１．３〜１．５μｍのレジス
ト４を塗布し、ｍｌンタクト孔形成領域に開１１部を形
成する。At the same time, a resist 4 having a thickness of 1.3 to 1.5 μm is applied thereto, and an opening 11 is formed in the ml contact hole formation region.
第１図（２）において、レジストパターンをマスクにし
て、等方性エツチングによりポリＳｉ層３をアンダーカ
ットする。In FIG. 1(2), the poly-Si layer 3 is undercut by isotropic etching using the resist pattern as a mask.
ポリＳｉの等方性エツチングの条件は、エツチングガス
として四弗化炭素（ＣＦ４）→−酸素（０□）をＩＴｏ
ｒｒに減圧して、周波数２．４５Ｇｌｌｚの電力をＩＫ
Ｗ加えて行う、マイクロ波励起によるプラズマエツチン
グによる。The conditions for isotropic etching of poly-Si are as follows: Carbon tetrafluoride (CF4) → -oxygen (0□) is used as the etching gas.
Reduce the pressure to rr and IK the power with a frequency of 2.45Gllz
By plasma etching using microwave excitation in addition to W.
第１図（３）においζ、異方性エツチングによりｎ−ｐ
ｓｃ層２を半分程度の厚さにする。Figure 1 (3) Odor ζ, n-p by anisotropic etching
The thickness of the sc layer 2 is reduced to about half.
ｎ−ｐｓｃの異方性エツチングの条件は、エツチングガ
スとして三弗化メタン（ＣＩＩＦ３） ＋ ０２を（１
，４Ｔｏｒｒに減圧して、周波数１３．５６Ｍ１ｌｚの
電力を５００−加えて行う、Ｉ？ＩＨによる。The conditions for anisotropic etching of n-psc are as follows: methane trifluoride (CIIF3) + 02 (1
I? By IH.
第１図（４）において、レジスト４を除去後、ポリＳｉ
層３をマスクにして、異方性エツチングにより＋１−Ｐ
ＳＧ層２を下地１が露出するまで除去する。In FIG. 1 (4), after removing the resist 4, the poly-Si
+1-P by anisotropic etching using layer 3 as a mask
SG layer 2 is removed until base 1 is exposed.
ロー１１５Ｇの異方性エツチングの条件は前工程と同様
である。The conditions for anisotropic etching of the row 115G are the same as in the previous step.
レジストの除去条件は、エツチングガスとして０２をｌ
Ｔｏｒｒに減圧して、周波数２．４５ＧＨｚの電力を
ＩＫＷ加えて行う、マイクロ波励起によるプラズマアッ
シングによる。The conditions for removing the resist are 02 l as etching gas.
Plasma ashing using microwave excitation is performed by reducing the pressure to Torr and applying IKW power with a frequency of 2.45 GHz.
第１図（５）において、エツチング後は図示のように段
差の緩和された断面形状を有するコンタクト孔が得られ
る。In FIG. 1(5), after etching, a contact hole having a cross-sectional shape with a reduced step as shown in the figure is obtained.
つぎに、ポリＳｉ層３を除去する。Next, poly-Si layer 3 is removed.
第１図（６）において、コンタクト孔を覆って配線層と
してアルミニウム（＾１）層５を形成する。In FIG. 1(6), an aluminum (^1) layer 5 is formed as a wiring layer covering the contact hole.
第２図＋１１〜（４）は第２の発明によるコンタクト孔
の形成方法を工程順に説明する断面図である。FIGS. 2+11 to (4) are cross-sectional views illustrating the method of forming a contact hole according to the second invention in the order of steps.
第２図（１）において、１は下地で、例えばＳｉ基板で
、この上にＣｖＩ′１法により、絶縁層として厚さ１μ
ｍの１ｌ−ＰＳＧ層２、マスク層として厚さ４０００人
のポリＳｉ層３を順次被着する。In Fig. 2 (1), 1 is a base, for example, a Si substrate, and an insulating layer is formed on this by CvI'1 method to a thickness of 1 μm.
A 1l-PSG layer 2 of 1.0 m thick and a 4000 m thick poly-Si layer 3 as a mask layer are successively deposited.
つぎに、その−１−に厚さ１．３〜１．５μｍのレジス
ト４を塗布し、二ｌンタクト孔形成領域に開「１部を形
成する。Next, a resist 4 having a thickness of 1.3 to 1.5 .mu.m is applied to the -1-, and an opening 1 is formed in the contact hole forming area.
第２図＋２１において、レジストパターンをマスクにし
て、等方性エツチングによりポリＳｉ層３をアンダーカ
ットする。In FIG. 2+21, the poly-Si layer 3 is undercut by isotropic etching using the resist pattern as a mask.
同時に、ｎ−ｐｓｃ層２も一部エソチングして凹部を形
成する。At the same time, a portion of the n-psc layer 2 is also etched to form a recess.
第２図（３）において、レジスト４を除去しないでこれ
をマスクにして、異方性エツチングによりローＰＳＧ層
２を下地１が露出するまで除去する。In FIG. 2(3), without removing the resist 4, using it as a mask, the low PSG layer 2 is removed by anisotropic etching until the base 1 is exposed.
つぎに、レジスト４、およびポリＳｉ層３を除去する。Next, the resist 4 and poly-Si layer 3 are removed.
第２図（４）において、図示のように段差の緩和された
断面形状を有する二１ンタクト孔が得られる。In FIG. 2(4), a contact hole 21 having a cross-sectional shape with a reduced step as shown in the figure is obtained.
この後、第１図（６）と同様にコンタクト孔を覆って配
線層を形成する。Thereafter, a wiring layer is formed to cover the contact hole in the same manner as in FIG. 1(6).
以上詳細に説明したように本発明による一１ンタクｌ孔
の形成方法では、デバイスの微細化にともないｍｌノン
タクト孔小さくなっても、配線層の段差被覆がよく、断
線の危険が少ない。As described above in detail, in the method for forming a 11-tact hole according to the present invention, even if the ml non-tact hole becomes smaller with the miniaturization of devices, the step coverage of the wiring layer is good and there is little risk of disconnection.
第１図（１）〜（６）は第１の本発明によるコンタクト
孔の形成方法を工程順に説明する断面図、第２図（１，
１〜（４）は第２の発明によるコンタクト孔の形成方法
を工程順に説明ゴる断面図、第３図（１）、（２）は従
来例による改良されたコンタクト孔形成方法である。
図において、
１は下地で、例えばＳｔ基板、
２は絶縁層でＤ−ＰＳＧ層、
３はマスク層でポリＳｉ層、
４はレジスト、
５は配線層でＡ１層
である。
１゛１、埋入ｆ「理士井桁貞−
第１の茫Ｅｒ目の１杢’ｐＥｇ、蛙、■目１３止作叫ト
ｄ盛１ 図
卒２の介ト巳Ｈの工Ｋａ畠ギ（ＢＨわ可イ［雨１２１嵜
２ 圀FIGS. 1 (1) to (6) are cross-sectional views explaining the method of forming a contact hole according to the first invention in the order of steps, and FIGS.
1 to 4 are cross-sectional views explaining the method of forming a contact hole according to the second invention in the order of steps, and FIGS. 3(1) and 3(2) show an improved method of forming a contact hole according to the conventional example. In the figure, 1 is a base, for example, an St substrate, 2 is an insulating layer, which is a D-PSG layer, 3 is a mask layer, which is a poly-Si layer, 4 is a resist, and 5 is a wiring layer, which is an A1 layer. 1゛1, Embedded f ``Roshi Igetasada - 1st eye 1 杢'pEg, frog, BH Wakaii [Ame 121 嵜2 圀
Claims (14)
）と、レジスト（４）とを順次被着し、該レジスト（４
）のコンタクト孔形成領域に開口部を形成し、 等方性エッチングにより、該マスク層（３）を該開口部
の面積より大きく除去し、 異方性エッチングにより、該絶縁層（２）を略該開口部
の面積で厚さ方向に厚さの途中までを除去し、レジスト
（４）を除去して、該マスク層（３）をマスクにした異
方性エッチングにより、該絶縁層（２）を除去して該下
地（１）を露出させる工程を含むことを特徴とする半導
体装置の製造方法。(1) On the base (1), insulating layer (2) and mask layer (3)
) and resist (4) are sequentially deposited, and the resist (4) is deposited in sequence.
), an opening is formed in the contact hole formation region, the mask layer (3) is removed by isotropic etching to a size larger than the area of the opening, and the insulating layer (2) is approximately removed by anisotropic etching. The area of the opening is removed halfway through the thickness in the thickness direction, the resist (4) is removed, and the insulating layer (2) is etched by anisotropic etching using the mask layer (3) as a mask. 1. A method for manufacturing a semiconductor device, comprising the step of removing the base (1) to expose the base (1).
）と、レジスト（４）とを順次被着し、該レジスト（４
）のコンタクト孔形成領域に開口部を形成し、 等方性エッチングにより、該マスク層（３）を該開口部
の面積より大きく除去し、かつ該絶縁層（２）の一部を
除去し、 異方性エッチングにより、該絶縁層（２）を除去して該
下地（１）を露出させる工程を含むことを特徴とする半
導体装置の製造方法。(2) An insulating layer (2) and a mask layer (3) are placed on the base (1).
) and resist (4) are sequentially deposited, and the resist (4) is deposited in sequence.
), forming an opening in the contact hole formation region, removing the mask layer (3) to a larger area than the opening by isotropic etching, and removing a part of the insulating layer (2); A method for manufacturing a semiconductor device, comprising the step of removing the insulating layer (2) to expose the base (1) by anisotropic etching.
する特許請求の範囲第１項記載の半導体装置の製造方法
。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the base (1) is a semiconductor substrate.
層であることを特徴とする特許請求の範囲第１項記載の
半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein the base (1) is a conductive layer deposited on a semiconductor substrate.
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(5) The method for manufacturing a semiconductor device according to claim 1, wherein the mask layer (3) is a polycrystalline silicon layer.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(6) The method of manufacturing a semiconductor device according to claim 1, wherein the mask layer (3) is a silicon nitride layer.
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(7) The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer (2) is a phosphosilicate glass layer.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(8) The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer (2) is a silicon dioxide layer.
する特許請求の範囲第２項記載の半導体装置の製造方法
。(9) The method for manufacturing a semiconductor device according to claim 2, wherein the base (1) is a semiconductor substrate.
電層であることを特徴とする特許請求の範囲第２項記載
の半導体装置の製造方法。(10) The method of manufacturing a semiconductor device according to claim 2, wherein the base (1) is a conductive layer deposited on a semiconductor substrate.
を特徴とする特許請求の範囲第２項記載の半導体装置の
製造方法。(11) The method for manufacturing a semiconductor device according to claim 2, wherein the mask layer (3) is a polycrystalline silicon layer.
特徴とする特許請求の範囲第２項記載の半導体装置の製
造方法。(12) The method for manufacturing a semiconductor device according to claim 2, wherein the mask layer (3) is a silicon nitride layer.
を特徴とする特許請求の範囲第２項記載の半導体装置の
製造方法。(13) The method of manufacturing a semiconductor device according to claim 2, wherein the insulating layer (2) is a phosphosilicate glass layer.
特徴とする特許請求の範囲第２項記載の半導体装置の製
造方法。(14) The method for manufacturing a semiconductor device according to claim 2, wherein the insulating layer (2) is a silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22520185A JPS6285444A (en) | 1985-10-09 | 1985-10-09 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22520185A JPS6285444A (en) | 1985-10-09 | 1985-10-09 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6285444A true JPS6285444A (en) | 1987-04-18 |
Family
ID=16825558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22520185A Pending JPS6285444A (en) | 1985-10-09 | 1985-10-09 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6285444A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63271957A (en) * | 1987-04-28 | 1988-11-09 | Sony Corp | Formation of multilayer interconnection |
| US5148184A (en) * | 1990-04-23 | 1992-09-15 | Sanyo Electric Co., Ltd. | Method of controlling printed density in thermal transfer recording |
| US5354716A (en) * | 1990-05-02 | 1994-10-11 | Nec Electronics, Inc. | Method for forming a DRAM memory cell with tapered capacitor electrodes |
| US5510294A (en) * | 1991-12-31 | 1996-04-23 | Sgs-Thomson Microelectronics, Inc. | Method of forming vias for multilevel metallization |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60755A (en) * | 1983-06-16 | 1985-01-05 | Pioneer Electronic Corp | Formation of through hole |
| JPS6196729A (en) * | 1984-10-17 | 1986-05-15 | Oki Electric Ind Co Ltd | Contact hole forming process of semiconductor integrated circuit |
-
1985
- 1985-10-09 JP JP22520185A patent/JPS6285444A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60755A (en) * | 1983-06-16 | 1985-01-05 | Pioneer Electronic Corp | Formation of through hole |
| JPS6196729A (en) * | 1984-10-17 | 1986-05-15 | Oki Electric Ind Co Ltd | Contact hole forming process of semiconductor integrated circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63271957A (en) * | 1987-04-28 | 1988-11-09 | Sony Corp | Formation of multilayer interconnection |
| US5148184A (en) * | 1990-04-23 | 1992-09-15 | Sanyo Electric Co., Ltd. | Method of controlling printed density in thermal transfer recording |
| US5354716A (en) * | 1990-05-02 | 1994-10-11 | Nec Electronics, Inc. | Method for forming a DRAM memory cell with tapered capacitor electrodes |
| US5510294A (en) * | 1991-12-31 | 1996-04-23 | Sgs-Thomson Microelectronics, Inc. | Method of forming vias for multilevel metallization |
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