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JPS6284527A - Chip carrier - Google Patents

Chip carrier

Info

Publication number
JPS6284527A
JPS6284527A JP22448885A JP22448885A JPS6284527A JP S6284527 A JPS6284527 A JP S6284527A JP 22448885 A JP22448885 A JP 22448885A JP 22448885 A JP22448885 A JP 22448885A JP S6284527 A JPS6284527 A JP S6284527A
Authority
JP
Japan
Prior art keywords
chip
substrate
radiator plate
heat sink
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22448885A
Other languages
Japanese (ja)
Inventor
Mitsuru Nitta
満 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22448885A priority Critical patent/JPS6284527A/en
Priority to US06/916,361 priority patent/US4731699A/en
Priority to FR868614016A priority patent/FR2588419B1/en
Publication of JPS6284527A publication Critical patent/JPS6284527A/en
Pending legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve heat-dissipating properties, and to mount a large-power chip while enhancing workability by fitting a radiator plate to a pin disposed in upright to a substrate and directly joining the chip with the radiator plate. CONSTITUTION:With a substrate 1, four pins 11 and bonding electrodes 12 are formed to a chip loading surface. Connecting terminals with the outside are shaped to the back reverse to the chip loading surface, and connected to the bonding electrodes 12 in the inner layer of the substrate 1. Four fitting holes 21 are formed where corresponding to the pins 11 for the substrate 1 in a radiator plate 2. An integrated circuit and circuit terminals 31 thereof are shaped to a chip 3. Since the radiator plate 2 and the chip 3 are joined directly without clearances extending over a wide range through a thermal conductive material, heat dissipated from the chip 3 is dissipated easily to the radiator plate 2 through the thermal conductive material, thus remarkably improving heat-dissipating properties, then mounting of the large-power chip is enabled.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のパッケージに関し、特に放熱
性を改良したチップキャリアに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor integrated circuit, and more particularly to a chip carrier with improved heat dissipation.

〔従来の技術〕[Conventional technology]

従来、この種のチップキャリアは、セラミックなどでで
きたキャリア本体の上面に、チップをグイボンディング
した後カバーを取付けるのみの構造(例えば、チップ 
キャリャーズーゼア アプリケイジョン アンドツユ−
チャー ディレクション、ジュー。ダブリュー、スタッ
フオード、アイ、イー、イー、イー、トラン、オン シ
ー、エイチ、エム、ティー、シーエイチェムチイー−4
,第2号、6月、1881または、チップ キャリャー
ズ:カミング フォース イン パツケイジング、ディ
ー、エリクソン エレクトロニック パツケイジング 
アンド プロダクション、1981年3月参町となって
いる。
Conventionally, this type of chip carrier has a structure in which the chip is bonded to the top surface of the carrier body made of ceramic or the like, and then a cover is attached (for example, the chip carrier is
Careers There Application and Tsuyu
Char Direction, Zhu. W, Staff Ode, I, E, E, E, Tran, On C, H, M, T, C H Chem Chi-4
, No. 2, June 1881, or Chip Carriers: Coming Force in Packaging, D. Erickson Electronic Packaging.
and Production, Sanmachi in March 1981.

〔解決すべき問題点〕[Problems to be solved]

従って、チップの半導体集積回路で発生した熱は、主に
キャリア本体を伝わって放散される。従って、キャリア
本体の材質、形状チップの接合面積などによって放熱量
が制限され、通常実装可能なチップの消費電力は1〜2
W程度までである。
Therefore, heat generated in the semiconductor integrated circuit of the chip is mainly dissipated through the carrier body. Therefore, the amount of heat dissipation is limited by the material of the carrier body, the bonding area of the shaped chip, etc., and the power consumption of a chip that can be mounted is usually 1 to 2.
It is up to about W.

しかるに、最近の高集積化、高速化された高性能チップ
では数W以上の消費電力のものが有り、また近い将来、
数十Wのものも予想される。これらの高性能、大電力チ
ップを従来のパッケージに実装しようとすると、チップ
の温度上昇によシ、信頼性を低下させたり、回路が焼損
してしまうなどの問題点がある。
However, recent highly integrated and high-speed high-performance chips have power consumption of several watts or more, and in the near future,
A power output of several tens of watts is also expected. When these high-performance, high-power chips are mounted in conventional packages, there are problems such as the chip's temperature rises, which reduces reliability and burns out the circuit.

〔問題点の解決手段〕[Means for solving problems]

本発明は上記問題点を解決したものであり、電極を有す
る所定面に複数のピンが立設されたキャリア本体と、集
積回路を有し、前記キャリア本体の所定面に対し、該集
積回路面を向けて載置され、該集積回路の端子を前記電
極にボンディングされたチップと、複数の嵌合穴を有し
、該各嵌合穴が夫々該各ピンに嵌合されて前記キャリア
本体に取付けられ、しかも前記チップに対し熱伝導材料
を介在して直接接合された放熱板とよシ構成してなるも
のである。
The present invention solves the above problems, and includes a carrier body in which a plurality of pins are erected on a predetermined surface having electrodes, and an integrated circuit, and the integrated circuit surface is The chip is mounted with the terminals of the integrated circuit facing the electrodes, and has a plurality of fitting holes, each of which is fitted with each of the pins to the carrier body. The heat sink is attached to the chip and is also configured with a heat sink directly bonded to the chip with a heat conductive material interposed therebetween.

〔実施例〕〔Example〕

次に、その実施例を第1図と共に説明する。 Next, an example thereof will be explained with reference to FIG.

第1図は本発明に係るチップキャリアの一実施例の分解
斜視図である。
FIG. 1 is an exploded perspective view of an embodiment of a chip carrier according to the present invention.

同図中、IFi本発明のチップキャリアのキャリア本体
としての基板で、チップ搭載面に、4本のピン11.お
よびボンディング電極12が形成されている。さらに図
示はしていないが、チップ搭g面と逆の裏面には外部と
の接続端子が有り、基板1の内層でボンディング電極1
2と接続されている。2ri放熱板で、基板lのピン1
1と対応する位置に4個の嵌合穴21が設けられている
。3は集積回路及びその回路端子31を有するチップで
ある。
In the figure, the IFi chip carrier of the present invention has four pins 11. and bonding electrodes 12 are formed. Furthermore, although not shown, there is a connection terminal with the outside on the back surface opposite to the chip mounting surface, and a bonding electrode 1 is provided on the inner layer of the substrate 1.
2 is connected. 2ri heat sink, pin 1 of board l
Four fitting holes 21 are provided at positions corresponding to 1. 3 is a chip having an integrated circuit and its circuit terminals 31;

次に、その組付につき説明する。まず基板lのチップ搭
載面に、チップ3をフェースダウン形式で取付け、端子
31を基板1のボンディング電極12にボンディングす
る。次に放熱板2をその各嵌合穴21が基板lの各ピン
11に嵌合するよう取付ける。この時、放熱板2とチッ
プ3の上面との間にハンダ、熱伝導性接着剤または熱伝
導性フンパウンドなどの熱伝導材料を供給介在させて接
合する。
Next, the assembly will be explained. First, the chip 3 is mounted face down on the chip mounting surface of the substrate 1, and the terminals 31 are bonded to the bonding electrodes 12 of the substrate 1. Next, the heat sink 2 is attached so that each of its fitting holes 21 fits into each pin 11 of the board 1. At this time, a thermally conductive material such as solder, thermally conductive adhesive, or thermally conductive powder is interposed between the heat sink 2 and the upper surface of the chip 3 to bond them.

これによれば、放熱板2は基板1のピン11に嵌合させ
ているため、放熱板2の位置が安定し、チップ3の高さ
にバラツキがあっても放熱板2を上下にスライドさせ容
易にチップ3の上面に沿わせることができ、両者2.3
の接合作業は容易でろ石。
According to this, since the heat sink 2 is fitted to the pin 11 of the substrate 1, the position of the heat sink 2 is stable, and even if the height of the chip 3 varies, the heat sink 2 can be slid up and down. It can be easily placed along the top surface of the chip 3, and both 2.3
It is easy to join the stones.

又放熱板2及びチップ3は熱伝導材料を介して広範囲に
直接隙間な(接合されるので、チップ3から発した熱は
、上記熱伝導材料を介して容易に放熱板2に放熱され、
放熱性が著しく向上し、大電力チップを実装することが
できる。
Furthermore, since the heat sink 2 and the chip 3 are directly connected to each other over a wide area through a heat conductive material, the heat generated from the chip 3 is easily radiated to the heat sink 2 through the heat conductive material.
Heat dissipation is significantly improved and high power chips can be mounted.

尚上記実施例では、放熱板2F′i単妃平板状のものと
しているが、フィンを付加して強制空冷とし一層放熱性
を高めてもよく、又放熱板2をキャビティ状にしてチッ
プ3を封止するようにしてもよい。
In the above embodiment, the heat sink 2F'i is shaped like a single flat plate, but fins may be added to provide forced air cooling to further improve heat dissipation, or the heat sink 2 may be shaped like a cavity to support the chip 3. It may be sealed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、基板に立設したピンに
放熱板を嵌合しかつ放熱板に直接チップが接合する構造
となるため、放熱性が良好となり大電力チップの実装が
可能となり、又放熱板の取付けをピンとの嵌合したこと
により、チップ高さのバラツキに対して、放熱板をスラ
イドさせてチップ裏面と放熱板とを容易に接合すること
ができ作業性を向上しうるなどの効果がある。
As explained above, the present invention has a structure in which the heat sink is fitted onto the pins set up on the substrate and the chip is directly bonded to the heat sink, so heat dissipation is good and high power chips can be mounted. In addition, by fitting the heat sink with the pins, the heat sink can be easily slid and the back side of the chip and the heat sink can be easily joined, even with variations in chip height, improving work efficiency. There are effects such as

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係るチップキャリアの一実施例の分解
斜視図である。 1・・・基板        2・・・放熱板3・・・
チップ       11・・・ピン】2・・・ボンデ
ィング電極  21・・・嵌合穴31・・・端子
FIG. 1 is an exploded perspective view of an embodiment of a chip carrier according to the present invention. 1... Board 2... Heat sink 3...
Chip 11... Pin] 2... Bonding electrode 21... Fitting hole 31... Terminal

Claims (1)

【特許請求の範囲】[Claims] 電極を有する所定面に複数のピンが立設されたキャリア
本体と、集積回路を有し、前記キャリア本体の所定面に
対し、該集積回路面を向けて載置され、該集積回路の端
子を前記電極にボンディングされたチップと、複数の嵌
合穴を有し、該各嵌合穴が夫々該各ピンに嵌合されて前
記キャリア本体に取付けられ、しかも前記チップに対し
熱伝導材料を介在して直接接合された放熱板とより構成
してなることを特徴とするチップキャリア。
It has a carrier body with a plurality of pins erected on a predetermined surface having electrodes, and an integrated circuit, and is placed with the integrated circuit surface facing the predetermined surface of the carrier body, and has terminals of the integrated circuit. The chip has a chip bonded to the electrode and a plurality of fitting holes, each of the fitting holes is fitted with each pin to be attached to the carrier body, and a thermally conductive material is interposed with respect to the chip. A chip carrier characterized by comprising a heat sink and a heat sink directly bonded to each other.
JP22448885A 1985-10-08 1985-10-08 Chip carrier Pending JPS6284527A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP22448885A JPS6284527A (en) 1985-10-08 1985-10-08 Chip carrier
US06/916,361 US4731699A (en) 1985-10-08 1986-10-07 Mounting structure for a chip
FR868614016A FR2588419B1 (en) 1985-10-08 1986-10-08 MOUNTING STRUCTURE FOR INTEGRATED CIRCUIT CHIP

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22448885A JPS6284527A (en) 1985-10-08 1985-10-08 Chip carrier

Publications (1)

Publication Number Publication Date
JPS6284527A true JPS6284527A (en) 1987-04-18

Family

ID=16814579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22448885A Pending JPS6284527A (en) 1985-10-08 1985-10-08 Chip carrier

Country Status (1)

Country Link
JP (1) JPS6284527A (en)

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