JPS6280750A - Data transfer device for system bus - Google Patents

Abstract

PURPOSE:To simplify hardware by providing each module with a pair of an address coincidence detecting circuit and a transfer control part and forming a bus selecting means for selecting a bus to be used for data transfer out of plural buses. CONSTITUTION:In a transfer control block of each module 14 constituting a general system, a sector 112 and a sector 213 (bus selecting means) select a system bus, i.e. a bus A8 or B9. A response side request stage ready signal 7 is used for the hand shaking of a request stage. A response side request stage status signal 15 indicates the status of a response side module 14 at the time of request stage hand shaking. A request stage indicating signal 4 is directly inputted to a transfer control part 11 without passing the selector 213.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device for a system bus used in a microcomputer system or the like.

[Conventional technology]

Figure 3 shows, for example, “Intel Multipath II (M[几TI
BUS II) Bus Architecture Specification Manual” (Intel Japan Co., Ltd., published in 1985, pp. 31-35)
3 is a time chart showing a data transfer cycle in a set of system buses 100 shown in FIG.

In FIG. 3, 1 indicates an address/data signal on the system bus ioo, 2 is a fixed address, and 3 is fixed data. 4.5.6 is the above system bus 10
0 is a transfer control signal, 4 is a request stage instruction signal, 5 is a request side ready signal, and 6 is a response side ready signal.

FIG. 4 is a block diagram showing the detailed configuration of the module 14 for realizing the transfer cycle of the system bus 100 shown in FIG. 3 above. In the figure, 10 is the address-number part, 1) is the transfer control part, and 21.24 to 2
6 indicates a signal line of the system bus.

FIG. 5 is a configuration diagram of a system having two sets of independent system buses, path A8 and bus B9 in the figure.
Two sets of system buses are configured. Further, reference numeral 14 is a module, which is commonly connected to path A8 and path B9, respectively. Each module 14 is connected to bus A8. Bus B9
A plurality of sets of transfer control units 1) and address/number configuration circuits 10 shown in FIG. 5 are provided corresponding to the two sets of system buses.

Next, the operation will be explained. In the request stage of the transfer cycle shown in FIG. 3, the request side module 14 that performs data transfer outputs a fixed address 2 on the address/data signal line 1, and also outputs a request stage signal 4a as a control signal for a certain period of time. do. At this time, all other modules 14 connected to the same bus A or B, 8 or 9 shown in FIG. 10, only the module 14 whose υ address matches becomes responsive. Then, when the request side module 14 disables the request stage signal 4a and enters the response stage, each time the confirmed data 3 is transferred via the signal line 2 of the address/data signal 1,
A handshake is performed between the requesting module 14 and the responding module 14. That is, for each data transfer, the requesting module 14 outputs the requesting ready signal 5 and the responding module 14 outputs the responding ready signal 6, and at the same time, each module 14 confirms the ready signal 5 of the other module 14. In particular, it synchronizes data transfers and checks for transfer errors.

[Problem that the invention seeks to solve]

Conventional system bus data transfer devices are configured as described above, so when configured with multiple independent system buses, an address/number configuration circuit and a transfer control unit are required for each bus. Each control circuit requires one set of control circuits, which poses problems such as the hardware becomes complex and the circuit becomes large-scale.

This invention was made in order to solve the above-mentioned problems, and aims to provide a system bus data transfer device that can transfer data with a simple hardware configuration in a system having a plurality of independent system buses. purpose.

[Means for solving problems]

The system bus data transfer device according to the present invention includes a set of an address/number configuration circuit and a transfer control section in each module, and bus selection means for selecting a path for data transfer from a plurality of buses. It is equipped with the following.

[For production]

Since the system bus data transfer device according to the present invention uses the bus selection means to select data transfer from multiple buses, each module can be configured as a set of an address/number configuration circuit and a transfer control section. becomes.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the transfer control block of each module 14 in a general system configuration, and two selectors, selector 1) 2 and selector 213 (bus selection means), select the system bus, that is, bus A8. The case where bus B9 is selected is shown. In the figure, 7 is a response 9Ill request stage ready signal, which is used to perform handshaking at the request stage.

15 is a response side request stage status signal, which is a signal indicating the status of the response side module 14 during the request stage handshake. The request stage instruction signal 4 is sent to the selector 21
3 directly to the transfer control unit 1). FIG. 2 shows a data transfer cycle in the configuration of FIG.

Next, the operation will be explained. First, one cycle of data transfer is performed using only one of the buses A8 and B9 shown in FIG.

Transfer control unit 1) selects bus A8 or B9 to be used for transfer using selector 1) 2 and selector 213.

However, the request stage instruction signal 4 of each bus A, B8t or 9
is directly input to the transfer control unit 1), and the module 1
4 is either bus A.

Even when transferring using B8 or 9,
Request stage indication signal 4 from other bus A, B8 or 9
It is possible to monitor the

Here, an example of a data transfer operation using bus A8 will be given and explained according to its transfer cycle.

The requesting module 14 outputs the request stage signal 4 along with the address 2 on the deterministic bus A8.

When all other modules 14 connected to the same bus A, B8 or 9 confirm the request stage signal 4, the address-number construction circuit 10 determines whether the addresses match. At this time, the module 14 performing the data transfer operation on the bus B9 receives the request stage signal 4.
, interrupt the transfer operation, and select selector 1).
After changing the designations of 2 and selector 213 to the bus A8 side, it is determined whether the addresses match. For this reason, there is a time delay in the module 14 performing the transfer operation compared to other modules 14 until the address match determination is completed.

Therefore, in order to synchronize the operations between the requesting module 14 and the responding module 14, the only responding module 14 that has detected an address match will respond to the request phase signal 4 output by the requesting module 14. In response, the response side request stage ready signal 7 is output, and the request side module 14
A request stage handshake is performed with the At this time, if the responding module is able to respond to the transfer request via bus A8, after handshaking in the request stage, the process moves to the response stage, where the requesting module 14 and the responding module 14 exchange a response. The finalized data 3 is transferred while performing a staged handshake. On the other hand, the responding module 14
When the responding module 14 is unable to respond to the transfer request via the bus A8, that is, when the responding module 14 suspends the transfer operation via the bus B9, the responding module 14
At the time of the request stage handshake, after transmitting information such as that a response is not possible to the request side module through the response side request stage status signal 15, processing such as resuming the transfer operation via the bus B9 is performed.

When the requesting module receives this information, it performs processing such as canceling the transfer or retrying the transfer depending on the content.

In the above embodiment, bus A8. Although the explanation has been made of a system bus consisting of two buses, bus B9, by increasing the number of selection targets of selector 1) 2 and selector 213, a system consisting of any number of system buses can be realized. Applicable to In addition, although a case has been described in which a dedicated response-side request stage ready signal 7 is used for the handshake in the request stage, other signals can be used as long as the response-side module 14 outputs the signal in the request stage and the request-side module 14 can confirm it. For example, the same signal line as the response side ready signal 6 may be used.

Furthermore, the response-side request stage status signal 15 may be any other signal as long as it can notify the request-side module 14 of information such as whether the response-side module 14 can respond in the request stage.

〔Effect of the invention〕

As described above, according to the present invention, in a system having a plurality of buses and a plurality of modules, each module is provided with a bus selection means for selecting data transfer from a plurality of buses. It can be constructed by providing one set of an address/number configuration circuit and a transfer control section, and has the effect of simplifying the hardware of the module.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system bus data transfer control device showing an embodiment of the present invention, FIG. 2 is a time chart showing a transfer cycle of data transfer according to the configuration of FIG. 1, and FIG. FIG. 4 is a time chart showing an example of a data transfer cycle in a conventional data transfer device, FIG. 4 is a block diagram showing a conventional transfer control device, and FIG. 5 is a system configuration diagram showing a general data transfer system. In the figure, 1) is a transfer control unit, 12 is a selector 1 (bus selection means), 13 is a selector 2 (bus selection means), 1
4 is a module. In each figure, the same reference numerals indicate the same or similar parts.

Claims (3)

[Claims] (1) In a system bus data transfer device comprising a system bus consisting of a plurality of buses through which signals such as address data and transfer data are transferred, and a plurality of modules commonly connected from this system bus, Each module includes an address match detection circuit that determines whether the address data matches the address data of its own module;
A system bus comprising a set of transfer control units that control data transfer on the system bus, and bus selection means that selects a bus for performing the data transfer from the plurality of buses. data transfer equipment. (2) The system bus data transfer device according to claim 1, wherein the transfer control unit is configured to perform handshake transfer at an initial point in time during a data transfer request or response. (3) The system bus data transfer device according to claim 2, wherein the transfer control unit is configured to send a status signal for handshake transfer when responding to a data transfer.