JPS6276557A - Insulated gate type self turn-off element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an insulated gate self-turn-off element having a pnpn thyristor structure and performing on/off control using a MOS gate.

[Technical background of the invention and its problems]

As an insulated gate type self-turn-off element, the one shown in FIG. 4 is conventionally known. This is the n-type emitter layer 6
1, an n-type base layer 63 and an n-type emitter layer 64 are formed in this n-type base layer 62.
The thyristor is basically a thyristor having a pnpn structure in which a cathode electrode 65 is formed in an n-type emitter layer and an anode electrode 66 is formed in an n-type emitter layer 61. By using the surface of the n-type base layer 63 between the n-type emitter layer 64 and the n-type base layer 62 as a channel region 73 and forming a gate electrode 68 thereon via a gate insulating film 67, a turn-on MOS gate G1 is formed. It consists of Further, the n-type layer 6 is adjacent to the n-type emitter layer 64.
9, and a p-type base between these! ! A gate electrode 71 is formed on the surface of 63 as a channel region 74 via a gate insulator 170, and a turn-off MOS gate G is formed.
2. The n+ type layer 69 is short-circuited to the n-type base layer 63 by an electrode 72.

The operation of this element is as follows. When a positive voltage is applied to the turn-on gate G1, the channels 1a73 become conductive, and electrons are injected from the n-type emitter layer 64 to the n-type base 1ii62, thereby turning on the thyristor. On the other hand, when the voltage of the gate G1 is set to zero and a positive voltage is applied to the turn-off gate G2, the n-type emitter layer 64 is connected to the channel region 74, the n-type layer 69. It is short-circuited to the n-type base 1163 through the electrode 72. This turns off the thyristor.

FIG. 5 shows a conventional example in which the element shown in FIG. 4 is modified.

This is achieved by combining n-channel and n-channel MOSFETs that control on/off of the thyristor.
Combine MOS gates into one.

There is. ρ type emitter 1181. n-type base layer 82° n-type base layer 83. The basic structure having a 411 structure of an n-type emitter 1184, a cathode electrode 85 and an anode electrode 86 is the same as in FIG. The difference from Figure 4 is that n
A p-type 1i 187 is provided at the end of the type emitter layer 84, and this n-type layer 87 is connected to the n-type emitter layer 8 by the cathode electrode 85.
4, and a gate electrode 89 is continuously formed on the surface of the region sandwiched between the p-type base layer 187 and the n-type base layer 82 via a gate insulator 1188, thereby forming one MOS gate G. That's true. A channel region 90 between the n-type emitter layer 84 and the n-type base 1F182 is for turn-on, and a channel region 91 between the n-type layer 87 and the n-type base layer 83 is for turn-off.

In this device, when a positive voltage is applied to the MOS gate G, the channels [90 are made conductive and the thyristor is turned on as in the case of FIG. 4. When a negative voltage is applied to the same MOS gate G, the channel region 91 becomes conductive, the n-type emitter layer 84 and the p-type base layer 83 are short-circuited, and the thyristor is turned off.

These conventional self-turn-off devices have the following drawbacks. The first is that the turn-off operation is difficult. Looking at the turn-off operation of the device shown in FIG. 4, when the channel region 74 is made conductive, the portion of the channel region 73 for turn-on among the junction surfaces of the n-type emitter layer 64 and the n-type base layer 63 is turned off most slowly. do. This is because the n-type emitter layer 64 is short-circuited to the n-type base layer 63 through the n-type layer 691 electrode 72 via the channel region 74 on the opposite side of the channel region 73, so that the potential of this electrode 72 is lower than that of the n-type base layer. This is because it is transmitted through the lateral resistance 63 to the channel region 73 most slowly. If the lateral voltage drop within the n-type base 1163 is large, short-circuiting between the n-type base layer 63 and the n-type emitter layer 64 will not be possible. In the device shown in FIG. 5, the channel region 91 at turn-off
When conductive, the off operation at the farthest position from the turn-on channel region 90 in the junction between the n-type emitter layer 84 and the n-type base layer 83 is delayed. If the M4 structure shown in the figure is configured symmetrically, the turn-off of the central part of the element will be delayed.

Also in this case, if the lateral resistance of the n-type base layer 83 is large, turn-off will not be possible. In both the structures shown in FIGS. 4 and 5, the resistance of the p-type base layer is large. That is, in FIG. 4, the n-type emitter t! Since there is a channel region 73 for turn-on on one side of 64, channel regions 74 for turn-off cannot be provided on both sides. Further, in FIG. 5, the p-type layer 87 is passed through the channel region 91 during turn-off.
Since the surface portion of the n-type base layer 83 that is electrically conductive with the substrate serves as a turn-on channel region 90, the resistance of this portion cannot be made similar. If n-type base layer 63.83
Increasing the impurity concentration increases the threshold voltage of the turn-on channel region, and increasing the diffusion depth also increases the resistance of the turn-on channel region.

The second drawback is that it is difficult to increase the breakdown voltage with these conventional device structures. This is because if the resistance of the n-type base layer is increased in order to increase the withstand voltage, a sufficient current cannot flow during turn-on.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an insulated gate type self-turn-off element that has improved turn-off ability and improved gate sensitivity during turn-on.

[Summary of the invention]

The present invention provides a self-turn-off element with a thyristor structure in which on-off control is performed by a MOS gate, in which a second conductivity type source layer is formed in a first conductivity type base layer separately from a second conductivity type emitter layer, and this source layer and A conductivity modulation MOSFE in which a source 'I4 pole is provided to short-circuit the first conductivity type base layer, and a MOS gate is formed on the surface of the first conductivity type base layer between the second conductivity type source layer and the second conductivity type base layer.
The present invention is characterized in that T is configured as a turn-on element, and a turn-off MOSFET is provided to short-circuit between the second conductivity type transmitter layer and the first conductivity type base layer.

[Effects of the Invention] According to the present invention, the second conductivity type source layer is provided separately from the second conductivity type emitter of the thyristor to form a conductivity modulation type MOSF.
By configuring the ET, only the portion of the first conductivity type base layer that becomes the channel region of the conductivity modulation type MOSFET is formed with a high resistance layer in a separate process, and the first conductivity type of the thyristor is
The conductive base layer resistance can be reduced and the turn-off ability can be increased. Furthermore, the present invention has an amplification gate structure in which the current of the conductivity modulation type MOSFET is supplied as the base current of the thyristor, so that the gate sensitivity at turn-on is high.

[Embodiments of the invention]

The present invention will be explained in detail below.

FIG. 1 shows the device structure of one embodiment. In this embodiment, p type is used as the first conductivity type, and n type is used as the second conductivity type. p-type emitter layer 11. n-type base layer 12.13.0
4 consisting of a type base layer 14 and an n-type emitter 1115
The thyristor structure, which has a layered structure and includes a cathode electrode (first main electrode) 16 and an anode electrode (second main electrode) 17, is basically the same as the conventional one. Further, an n-type base layer 18 is formed at the end of the n-type base layer 14 of the thyristor body so as to overlap this. This n-type base layer 18 has a lower impurity concentration and a shallower diffusion depth than the n-type base layer 14. Then, at the end of this n-type base layer 18,
type source layer 19 is formed, and this n type source If! 11
A source electrode 22 is formed to short-circuit the n-type base layer 18 and the n-type base layer 18, and a channel region 26 is formed on the surface of the n-type base layer 18 sandwiched between the n-type source layer 19 and the n-type base layer 13. Gate electrode 21 via gate insulating film 20
is formed to constitute a conductivity modulation type MOSFET. The gate electrode/pole 21 of this conductivity modulation type MOSFET becomes the turn-on gate G1. On the other hand, n-type emitter layer 1
5 is the source region, and on both sides n is the drain region.
A type layer 23 is provided, and a region between the n-type layer 23 and the n-type emitter layer 15 is used as a channel region 27, and a gate electrode 25 is formed thereon via a gate insulator 1124.
An n-channel MOSFET is configured. The source electrode 22 of the conductivity modulation type MOSFET is also connected to the n-type layer 23 of this MOSFET.

The gate electrode 25 of this MOSFET becomes the turn-off gate G2.

To explain a specific manufacturing process example of this element, the n-type base layer 13 is 120 to 150 Ω·α.

An n-type Si wafer with a thickness of 350 μm is prepared, and a high concentration n-type layer 12 of, for example, 30 μm and an n-type emitter layer 11 of 30 μm are formed by n+ diffusion and p+ diffusion.

Next, a p-type impurity is diffused to the opposite side of the wafer to form an n-type base layer 14.

After this, thermal oxidation is applied to the gate insulating film 20.
Then, about 5,000 polycrystalline silicon films are deposited to form gate electrodes 21 and 25. Next, using the gate electrodes 21 and 25 as part of a mask, the n-type emitter layer 15, the n-type base layer 18, the n-type source layer 19, and the n-type layer 23 are sequentially diffused. Finally, a cathode electrode, a source electrode 22, and an anode electrode 17 are formed to complete the process.

The operation of this element is as follows. Turn-on operation is M
This is done by applying a positive voltage to the OS gate G1.

This makes the channel region 26 conductive and the conduction modulation MOS
The FET is turned on and its source current is supplied to n-type base layers 18 and 14 via source electrode 22. This turns on the thyristor. Next, at turn-off, the voltage of MOS gate G1 is set to zero, and a positive voltage is applied to MOS gate G2. This allows n-channel MOS
The channel region 27 of the FET becomes conductive, and the n-type emitter layer 1
5 through this channel region 27, and the n-type layer 23 . It is short-circuited to the n-type base layers 18 and 14 via the source electrode 22 and turned off.

Thus, in the device of this embodiment, when turned on, the source 'R current of the conduction modulation type MOSFET becomes the base current of the thyristor, and the gate sensitivity is high based on the same principle as the amplification gate type thyristor.

Further, channel regions 27 for turn-off are formed on both sides of the n-type emitter layer 15, and conductivity modulation type M
Since the n-type base layer 18 of the OSFET and the n-type base layer 14 of the thyristor main body are formed in separate processes, the n-type base layer 14 can be formed without lowering the resistance of the n-type base layer 18.
resistance can be lowered. For these reasons, this device has a high turn-off ability.

FIG. 2 is a self-turn-off device according to another embodiment of the present invention. This device is constructed so that the entire device shown in FIG. 1 is used as an amplification stage, that is, as an auxiliary thyristor to drive a main thyristor formed separately. Therefore, the same reference numerals as in FIG. 1 are given to the parts corresponding to those in FIG. 1, and detailed explanation thereof will be omitted. The n-type base layer 28 of the main thyristor section is adjacent to the n-type base layer 14 of the auxiliary thyristor section.
and an n-type emitter layer 29 are formed, and a cathode electrode 3o is formed on this n-type emitter layer 29. N-type layers 32 are formed adjacent to the two n-type emitter layers on both sides of the main thyristor section, and these n-type emitters W429
A gate electrode 34 is formed on the substrate surface between the n-type layer 32 and the n-type layer 32 with a gate insulating film 33 interposed therebetween. This gate electrode 3
Reference numeral 4 is for turn-off, and is commonly connected to the turn-off gate electrode 25 of the auxiliary thyristor section. Further, an electrode 31 is provided to short-circuit between the n-type layer 32 and the n-type base layer 28, and this electrode 32 is connected to the cathode ff1 of the auxiliary thyristor section.
It is connected to tffi16.

In this element, when the auxiliary thyristor is turned on as explained in connection with the element in FIG. This turns on the main thyristor. The turn-off operation is performed by simultaneously applying a positive voltage to the gate electrode 22 on the auxiliary thyristor side and the gate electrode 34 on the main thyristor side to short-circuit both n-type emitter layers and p-type base layer at the same time. .

Therefore, in this element, the base current undergoes two stages of amplification during turn-on, and the gate sensitivity at turn-on becomes even higher than in the case of FIG.

FIG. 3 shows a self-turn-off device according to yet another embodiment of the present invention. This element is similar to the conventional element shown in FIG.
p-channel MOSFET for turn-off and turn-on
This is an improved device in which on-off control is performed by a single MOS gate by combining a MOS transistor and an n-channel NII OS FET.

The basic structure of the thyristor, which has a four-layer structure of an n-type emitter layer 41, an n-type base layer 42, 43, an n-type base layer 44, and an n-type emitter layer 45, and a cathode electrode 47 and an anode electrode 48, is unchanged from the conventional one.

A heavily doped n-type emitter layer 46 is formed under the cathode electrode 47 . An n-type base layer 49 is formed at the end of the n-type base layer 44 in a separate diffusion process. An n-type source lff150 is formed in this n-type base layer 49, and the surface of the n-type base layer 49 sandwiched between this n-type source layer 50 and n-type base layer 43 is used as a channel region 56, and a gate insulating film is formed thereon. A gate electrode 52 is formed through the gate electrode 51, and a source electrode 53 is formed to short-circuit between the n-type source layer 50 and the n-type base layer 49.
FET is configured. This conductivity modulation type MOSFET
constitutes an amplification gate section for turn-off control as in the previous embodiment. On the other hand, an n-type layer 58 serving as a source region is formed near the end of the n-type emitter layer 45.
8 and an n-type base layer 44 which becomes a drain region.
The surface of the type emitter layer 45 is used as a channel region 57, and gate insulation If! Gate electrode 55 via 154
is formed to constitute a p-channel MOSFET. This MOSFET is used for turn-off control. Note that the n-type layer 58 of this MOSFET is kept at the same potential as the n-type layer 46 by the cathode electrode 47. The gate electrode 55 of this MOSFET and the gate electrode 52 of the conductive modulation type MOSFET are commonly connected to form one MOS gate G.

The operation of this element is turned on by applying a positive voltage to the MOS gate G to turn on the conductivity modulation type MOS FET, and supplying its source current to the n-type base layer 44 as a base current. This is similar to the previous embodiment. At turn-off, a negative voltage is applied to the MOS gate G. This turns on the p-channel MOSFET and n
Type emitter @45 and p type base It! i44 is shorted and the device turns off.

In this embodiment as well, since the conductivity modulation type MOSFET acts as an amplification gate, high Gou1-sensitivity can be obtained at turn-on as in the previous embodiment.

Furthermore, the channel region 56 of the conductivity modulation type MOSFET does not enter the current path flowing through the MOSFET during turn-off. In addition, the n-type base layer 49 of the quadrupolar modulation MOSFET section is formed in a separate process from the n-type base layer 44 of the thyristor body.
Therefore, the resistance of the n-type base layer 44 can be made small, and the overlapping portion of the n-type base layers 44 and 49 has an even lower resistance, so the turn-off ability is extremely high. becomes.

The present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit thereof.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an insulated gate I-type self-turnoff device according to one embodiment of the present invention, FIG. 2 is a diagram showing an insulated gate type self-turnoff device according to another embodiment, and FIG. 3 is a diagram showing still another embodiment. FIGS. 4 and 5 are diagrams showing conventional insulated gate self-turn-off devices. DESCRIPTION OF SYMBOLS 11... N-type emitter layer, 12.13... N-type base layer, 14... N-type base layer, 15... N-type emitter layer, 16... Cathode electrode, 17... Anode electrode, 18... n-type base layer, 19... n-type source layer, 20... gate insulating film, 21... gate electrode, 2
2... Source electrode, 23... N-type layer (drain region), 24... Gate insulating film, 25... Gate electrode,
26...Channel region (conductivity modulation type MOSFET>,
27...Channel l [(n-channel MOSFET),
28. p-type base layer, 29...[)-type emitter layer,
30... Cathode electrode, 31... Short circuit electrode, 32...
... n-type layer (drain region), 33 ... gate insulating film, 34 ... gate electrode, 41 ... n-type emitter layer,
42.43...n-type base layer, 44...p-type base layer, 45.46...n-type emitter layer, 47...cathode current, 48...anode electrode, 49... -p type base layer, 50... n type source layer, 51... gate insulating film, 52... gate electrode, 53... source electrode, 54... gate insulating film, 55... gate electrode, 5
6... Channel region (conductivity modulation type MOSFET), 5
7... Channel region (p channel MO3FE), 5
8...n-type layer (source region). Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4

Claims (4)

[Claims] (1) having a second conductivity type base layer in contact with the first conductivity type emitter layer, the first conductivity type base layer and the second conductivity type emitter layer being diffused and formed on the surface of the second conductivity type base layer;
It has a thyristor structure in which a first main electrode is formed in the second conductivity type emitter layer and a second main electrode is formed in the first conductivity type emitter layer, and is configured to perform on/off control by a MOS gate. In the self-turn-off element, a second conductivity type source layer provided within the first conductivity type base layer separately from the second conductivity type emitter layer, and a source electrode shorting between this source layer and the first conductivity type base layer. , and a turn-on conductivity modulation type MOS having a MOS gate formed on the surface of the first conductivity type base layer in a region sandwiched between the second conductivity type source layer and the second conductivity type base layer.
An insulated gate self-turn-off element, characterized in that an FET and a turn-off MOSFET that short-circuits between the second conductivity type emitter layer and the first conductivity type base layer are integrally formed. (2) The turn-off MOSFET has the second conductivity type emitter layer as a source region, is formed in the first conductivity type base layer at a predetermined distance from the source region, and is connected to the source electrode of the conductivity modulation MOSFET. a second conductivity type drain region short-circuited with a first conductivity type base layer;
2. The insulated gate self-turn-off device according to claim 1, which is a second conductive channel MOSFET in which a MOS gate is formed between these source and drain regions. (3) the turn-off MOSFET has a first conductivity type source region formed in the second conductivity type emitter layer and short-circuited to the n-type emitter layer by the first main electrode;
The insulation according to claim 1, wherein the first conductive channel MOSFET is a first conductive channel MOSFET in which a MOS gate is formed on a second conductive type emitter layer sandwiched between the first conductive type source region and the first conductive type base layer. Gate type self turn-off element. (4) The first conductivity type base layer portion which becomes the channel region of the conductivity modulation MOSFET is formed by diffusion separately from the first conductivity type base layer of the thyristor body so as to overlap with the end portion of the first conductivity type base layer. The insulated gate self-turn-off device according to item 1.