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JPS627142A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS627142A
JPS627142A JP14749585A JP14749585A JPS627142A JP S627142 A JPS627142 A JP S627142A JP 14749585 A JP14749585 A JP 14749585A JP 14749585 A JP14749585 A JP 14749585A JP S627142 A JPS627142 A JP S627142A
Authority
JP
Japan
Prior art keywords
film
energy beam
semiconductor device
semiconductor
melted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14749585A
Other languages
Japanese (ja)
Inventor
Katsumi Takashima
高島 克巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP14749585A priority Critical patent/JPS627142A/en
Publication of JPS627142A publication Critical patent/JPS627142A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To flatten the surface of a semiconductor after melting and solidifying by forming a film capable of melting, emitting an energy beam to the film to once melt the film, and utilizing the fluidity of the melted film material. CONSTITUTION:When an energy beam 4 is emitted to a polysilicon film 3 having an irregular surface, the film 3 of the emitted portion is melted to form a melted region 5, the region 5 is moved by scanning the beam 4, and fluidized to resultantly flatten the surface. The film 3 may be formed of a material which is melted by emitting the energy beam, fluidized and resolidified such as preferably polysilicon used in an SOI technique. The beam 4 is preferably Ar<+> ion laser frequently used in a semiconductor manufacturing process, and can use an electron beam.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置の製造方法の改良に関し、更に詳細
には集積回路素子を作製した半導体の表面を平坦化する
と共に、上層デバイスと下層デバイスの相互干渉を防止
するようにした積層構造の半導体装置の作製に適した半
導体装置の製造方法に関するものである。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an improvement in a method for manufacturing a semiconductor device, and more specifically, to planarize the surface of a semiconductor fabricated with an integrated circuit element, and flatten the surface of a semiconductor fabricated with an integrated circuit element. The present invention relates to a method for manufacturing a semiconductor device suitable for manufacturing a semiconductor device having a stacked structure in which mutual interference between the two layers is prevented.

〈従来の技術〉 一般に集積回路を作シ込んだ半導体基板の表面には、回
路作成時の酸化膜や回路要素間を電気的に接続する配線
及び電極等の導電体のために凹凸が生じている。このよ
うな表面の凹凸は配線を多層に重ねた構造の半導体装置
や、高密度及び高機能化を進めるために開発が行なわれ
ている積層型半導体装置を作製する場合においては好ま
しいものではない。特に積層型半導体装置においては、
絶縁膜を介して能動層となる単結晶層を積層していくた
め、表面の段差及び凹凸は結晶成長工程やその結晶性に
悪影響を及ぼすことになる。
<Prior art> Generally, the surface of a semiconductor substrate on which an integrated circuit is fabricated has unevenness due to the oxide film during circuit fabrication and conductors such as wiring and electrodes that electrically connect circuit elements. There is. Such surface irregularities are not preferable when manufacturing a semiconductor device having a structure in which wiring is stacked in multiple layers, or a stacked semiconductor device which is being developed to achieve higher density and higher functionality. Especially in stacked semiconductor devices,
Since single-crystal layers serving as active layers are stacked with an insulating film interposed therebetween, surface steps and unevenness have a negative effect on the crystal growth process and its crystallinity.

このため、半導体層0表面形状を平坦にする方法が種々
開発され提案されている。
For this reason, various methods for flattening the surface shape of the semiconductor layer 0 have been developed and proposed.

その平坦化処理の代表的なものとして ■ 有機塗布膜と等速エツチングを用いたエッチパック
平坦化法、 ■ 無機塗布膜を形成して平坦化する方法、■ バイア
スヌパッタ法による膜堆積方法、が提案されている。
Typical flattening treatments include: ■ Etch pack flattening method using an organic coating film and constant-speed etching, ■ Method of forming an inorganic coating film and flattening it, ■ Film deposition method using bias putter method, is proposed.

上記■の方法は、基板表面に生じている凹凸にほぼ対応
して表面に凹凸の出現している絶縁膜上に有機塗布膜材
を表面が平坦になるように塗布して有機塗布膜を形成し
た後、有機塗布膜表面から等速エツチングを行なって、
当初の有機塗布膜の平坦な表面を絶縁膜に転写して、絶
縁膜をほぼ平坦にするものである。
The above method (■) forms an organic coating film by applying an organic coating film material so that the surface is flat on an insulating film whose surface has irregularities that roughly correspond to the irregularities occurring on the substrate surface. After that, isokinetic etching is performed from the surface of the organic coating film,
The flat surface of the original organic coating film is transferred to the insulating film to make the insulating film almost flat.

また上記■の方法は、表面に凹凸の生じている絶縁膜上
に絶縁材である無機塗布膜材を塗布して形成して、この
無機塗布膜によって絶縁膜表面の凹凸を滑らかにし、あ
るいは無機塗布膜表面からエツチングを行なって絶縁膜
をほぼ平坦にするものである。
In addition, in the method (2) above, an inorganic coating film material is applied as an insulating material on an insulating film with an uneven surface, and the unevenness on the surface of the insulating film is smoothed by this inorganic coating film. Etching is performed from the surface of the coating film to make the insulating film substantially flat.

〈発明が解決しようとする問題点〉 しかし、上記■あ方法にあっては、下地の凹凸パターン
が複雑かつ、その凹凸量が数種類にも及ぶ場合、このよ
うな下地の凹凸を平坦化するためには、有機膜の膜厚設
定やダミーパタ“−ンの形成など、プロセスが複雑であ
る。
<Problems to be Solved by the Invention> However, in the method (i) and (a) above, when the uneven pattern of the base is complex and there are several types of unevenness, it is difficult to flatten the unevenness of the base. The process is complicated, such as setting the thickness of the organic film and forming dummy patterns.

また、上記■の方法にあっては、有機膜に比して、無機
膜は厚膜を形成するのが困難であシ、所望の厚い膜を得
るためには、数回にわたって膜形問題があり、セたプロ
セスも煩雑である。
In addition, in the method (2) above, it is difficult to form a thick film with an inorganic film compared to an organic film, and in order to obtain a desired thick film, the film shape problem must be solved several times. Yes, and the setup process is complicated.

更に上記■の方法にあっては、完全な平坦化を達成する
ためには、スループットが上がらない等いずれの方法も
満足し得る方法とはいい難く、新規な平坦化方法の開発
が望まれていた。
Furthermore, in order to achieve complete planarization, none of the above methods can be said to be satisfactory, as the throughput does not increase, and the development of a new planarization method is desired. Ta.

本発明は、上記の点にかんがみて創案されたもので、簡
単なプロセスで平坦化処理を行りい得ると共に、上層デ
バイスと下層デバイスの相互干渉を防止し得るようにし
た半導体装置の製造方法を提供することを目的としてい
る。
The present invention has been devised in view of the above points, and is a method for manufacturing a semiconductor device that can perform planarization processing with a simple process and can prevent mutual interference between upper layer devices and lower layer devices. is intended to provide.

〈問題点を解決するための手段〉 上記の目的を達成するため、本発明の半導体装置の製造
方法は、デバイス形成後の半導体基板上の表面にある凹
凸を平坦化するために、その表面にレーザあるいは電子
ビーム等のエネルギービームの照射によって選択的に溶
融可能な膜(例えばポリシリコン膜等)を形成し、その
後エネルギービームを上記の膜に照射することにょシ、
その膜を一担溶融させ、その溶融した膜材の流動性を利
用して、溶融固化後半導体表面を平坦化する工程を含ん
でなるように構成している。
<Means for Solving the Problems> In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention provides a method for manufacturing a semiconductor device in which a semiconductor substrate is coated on the surface in order to flatten unevenness on the surface after device formation. Forming a film (for example, a polysilicon film, etc.) that can be selectively melted by irradiation with an energy beam such as a laser or an electron beam, and then irradiating the above film with the energy beam,
The method is configured to include a step of melting the film and flattening the semiconductor surface after melting and solidifying by utilizing the fluidity of the melted film material.

また後述する本発明の実施例によれば、本発明を実施し
た半導体装置は、層間の絶学層となる下地絶縁膜を形成
する工程と、レーザや電子ビーム等のエネルギービーム
の照射によって、選択的に溶融可能な導電膜(例えばド
〒ブトポリシリコン膜)を形成する工程と、この導電膜
にエネルギービームを照射して一担溶融させ、その流動
性を利用して溶融固化後半導体表面を平坦化する工程と
、この導電膜と上層デバイスとを絶縁分離するための絶
縁膜を形成する工程とを含んでなるように構成している
Further, according to the embodiments of the present invention to be described later, a semiconductor device implementing the present invention can be selectively manufactured by forming a base insulating film that serves as an insulating layer between layers and by irradiating an energy beam such as a laser or an electron beam. The process involves forming a conductive film (for example, a double polysilicon film) that can be melted automatically, and then irradiating this conductive film with an energy beam to melt it once, and using its fluidity to melt and solidify the semiconductor surface. The structure includes a planarization step and a step of forming an insulating film for insulating and separating this conductive film from the upper layer device.

く作 用〉 上記のような構成によシ、本発明はレーザや電子ビーム
などのエネルギービームによって選択的に溶融できる膜
を凹凸の生じた半導体表面に堆積し、その後エネルギー
ビームを上記の膜に照射してその膜を一担溶融させ、そ
の溶融した膜材の流動性を利用することによシ、溶融固
化後、半導体表面が平坦化される。
Function> In addition to the above-described structure, the present invention deposits a film that can be selectively melted by an energy beam such as a laser or an electron beam on a semiconductor surface having irregularities, and then applies the energy beam to the film. By irradiating the film to melt the film and utilizing the fluidity of the melted film material, the semiconductor surface is flattened after melting and solidification.

また、この平坦化層は上層デバイスと下層デバイス間の
相互干渉を防止する作用をなすと共に、上層デバイス形
成時のヒートシンクの役割を果たす。
Further, this planarization layer functions to prevent mutual interference between the upper layer device and the lower layer device, and also serves as a heat sink during formation of the upper layer device.

本発明における平坦化処理について更に説明すると、そ
の原理的作用は次の通りである。
To further explain the flattening process in the present invention, its principle operation is as follows.

一般に、レーザ光や電子ビーム等のエネルギービームを
試料面に照射すると、例えばレーザ光の場合、試料の物
質定数に応じた吸収や界面での反射、更には膜厚を調整
することにより、干渉等の効果も重ね合わさることによ
シ、試料を加熱することになる。このとき、その試料の
融点以上に加熱した場合には、ビーム照射部のみが溶融
状態になる。このときビームを走査させた場合、はぼビ
ームの走査速度と同一速度で液相部がビーム走査と一緒
に移動することになり、ビームが移動した後の液相部は
すみやかに冷却固化することになる。
In general, when an energy beam such as a laser beam or an electron beam is irradiated onto a sample surface, for example, in the case of a laser beam, interference can be caused by absorption depending on the material constants of the sample, reflection at an interface, and even by adjusting the film thickness. The effects of the above are also combined to heat the sample. At this time, if the sample is heated above its melting point, only the beam irradiated part becomes molten. If the beam is scanned at this time, the liquid phase will move at the same speed as the beam scanning speed, and the liquid phase will quickly cool and solidify after the beam has moved. become.

第1図は本発明における平坦化工程の原理を説明するた
めの図であシ、同図において1はシリコン基板、2は表
面に凹凸を有する絶縁膜(Si02)。
FIG. 1 is a diagram for explaining the principle of the planarization process in the present invention. In the figure, 1 is a silicon substrate, and 2 is an insulating film (Si02) having an uneven surface.

3は凹凸を有する表面上に堆積されたポリシリコン膜で
あり、この凹凸を有するポリシリコン膜にエネルギービ
ーム4を照射した場合、その照射部分のポリシリコン膜
3が溶融して溶融領域5が形成され、この溶融領域5は
エネルギービーム4の走査と共に移動すると共に流動し
、結果的に表面が平坦化されることになる。
Reference numeral 3 denotes a polysilicon film deposited on a surface having unevenness, and when the polysilicon film having unevenness is irradiated with an energy beam 4, the polysilicon film 3 in the irradiated part melts and a melted region 5 is formed. The melted region 5 moves and flows with the scanning of the energy beam 4, and as a result, the surface is flattened.

なお、膜3としてはエネルギービームの照射によって溶
融し、流動再固化する材料であれば良いが、例えばSo
 I (Siljcon On In5ulator)
技術において用いられるポリシリコンが好適寸あ・る。
The film 3 may be made of any material that melts and re-solidifies when irradiated with an energy beam; for example, Sodium
I (Siljcon On In5ulator)
The preferred size is polysilicon used in the technology.

またエネルギービーム4としては半導体製造プロセスに
おいて多く用いられているArイオンレーザを用いて好
適であるが、これに限定されるものではなく、例えば電
子ビーム等を用いることも可能である。
Further, as the energy beam 4, it is preferable to use an Ar ion laser, which is often used in semiconductor manufacturing processes, but the present invention is not limited to this, and it is also possible to use, for example, an electron beam.

〈実施例〉 以下、本発明の一実施例を図面を参照して詳細に説明す
る。
<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第2図(a)乃至(e)は、それぞれ本発明による一実
施例の1寝を説明するための半導体装置断面図である。
FIGS. 2(a) to 2(e) are sectional views of a semiconductor device, respectively, for explaining one embodiment of the present invention.

まず、第2図(a)に示すように半導体基板11にMO
S)ランジスタ等の回路素子を作シ込むと共に、各回路
要素間を導電体(高融点金属等の配線層)14によって
電気的に接続し、表面を絶縁膜15で被う。なお、12
は絶縁膜である。この゛ 状態で下地となっている半導
体基板110表面は、導電体14等によって凹凸が生じ
ているため、絶縁膜150表面には、それに対応した凹
凸が生じている。
First, as shown in FIG. 2(a), MO is applied to the semiconductor substrate 11.
S) Inserting circuit elements such as transistors, electrically connecting each circuit element with a conductor (wiring layer of high melting point metal, etc.) 14, and covering the surface with an insulating film 15. In addition, 12
is an insulating film. In this state, the surface of the underlying semiconductor substrate 110 has irregularities due to the conductor 14 and the like, so the surface of the insulating film 150 has corresponding irregularities.

次に、第2図(b)に示すように、絶縁膜15上に溶融
平坦化するための膜、例えばドープしたポリシリコン導
電膜(平坦化膜)16を堆積する。
Next, as shown in FIG. 2(b), a film for melting and planarizing, for example, a doped polysilicon conductive film (planarizing film) 16, is deposited on the insulating film 15.

次に第2図(c)に示すように表面全域をレーザビーム
等のエネルギービーム17によって走査り。
Next, as shown in FIG. 2(c), the entire surface is scanned with an energy beam 17 such as a laser beam.

てポリシリコン導電膜16を溶融し、流動再固化させて
第2図(d)に示すように平坦化をはかる。
The polysilicon conductive film 16 is melted and re-solidified in a fluidized manner to planarize it as shown in FIG. 2(d).

最後に第2図(e)に示2すように平坦化膜16上に層
間絶縁膜25を形成し、その上に2層目のデバイス20
を作製して工程を完了する。
Finally, as shown in FIG. 2(e), an interlayer insulating film 25 is formed on the planarization film 16, and a second layer of devices 20 is formed on it.
to complete the process.

また、半導体装置を3層構造に形成する場合には2N目
において、同様の平坦化処理を行なう。
Further, when a semiconductor device is formed to have a three-layer structure, a similar planarization process is performed at the 2Nth layer.

以下、4層、5層構造についても同様のことを繰返すこ
とになる。
Hereinafter, the same process will be repeated for the four-layer and five-layer structures.

上記一層目素子lOと2層目素子200間に位置する平
坦化膜(ポリシリコン導電膜)16はバッファ層として
の役目をなし、上下層のデバイス10及び20の電気的
干渉を防止すると共に、上層デバイス29を形成する際
のヒートシンクの役割を果すことになる。
The planarization film (polysilicon conductive film) 16 located between the first layer element 10 and the second layer element 200 serves as a buffer layer, and prevents electrical interference between the devices 10 and 20 in the upper and lower layers. It plays the role of a heat sink when forming the upper layer device 29.

上記のような工程を含んだ工程によって半導体装置を作
製することによシ、 ■ 表面が平坦に形成されるため加工精度が向上する。
By manufacturing a semiconductor device through a process including the steps described above, (1) the surface is formed flat, improving processing accuracy;

■ 表面が平坦であるため、配線や絶縁膜のクラック、
断線等が生じなくなる。
■ Because the surface is flat, cracks in wiring and insulating films,
Disconnection, etc. will not occur.

■ 2層目以降の能動層形成時に生じていた段差による
結晶成長阻害等の問題が解決され、均一で良質な単結晶
層を得ることが出来る。
(2) Problems such as inhibition of crystal growth due to steps that occurred during the formation of the second and subsequent active layers are solved, and a uniform and high-quality single crystal layer can be obtained.

■ 平坦化された導電膜が各能動層間に挿入されること
によシ、能動層間の電気的干渉が防止される。
(2) Electrical interference between active layers is prevented by inserting a flattened conductive film between each active layer.

■ 平坦化のために挿入された導電膜がバッファ層とし
て作用し、上層デバイス形成時のヒートシンクの役割を
果たすことになる。
■ The conductive film inserted for planarization acts as a buffer layer and serves as a heat sink when forming upper layer devices.

■ 単結晶層をはじめ、積層膜のストレヌが低減される
■ Reduces strain in laminated films, including single crystal layers.

■ プロセスの簡素化が期待できる。■ Simplification of the process can be expected.

等の利点が生じる。Benefits such as:

〈発明の効果〉 以上のように本発明によれば、従来プロセス上煩雑であ
った平坦化処理プロセスを簡素化することが出来る。
<Effects of the Invention> As described above, according to the present invention, it is possible to simplify the planarization process, which has conventionally been complicated.

また本発明によって作製された素子は積層デバイスの構
造として積層デバイス相互間の相互干渉を防止する構造
となる利点がある。
Further, the element manufactured according to the present invention has the advantage of having a structure of a laminated device that prevents mutual interference between the laminated devices.

また平坦化工程としてはレーザ等のエネルギービームの
照射のみで済むため、半導体装置の製造工程において追
加するマヌクは不要であり、製造プロセスが簡素化され
る。更にビーム照射による表面加熱を利用したものであ
るため、低温プロセスに適しておシ、結果として高品質
の多層構造のデバイスの作製が可能となる。
Further, since the planarization process requires only irradiation with an energy beam such as a laser, no additional manufacturer is required in the semiconductor device manufacturing process, and the manufacturing process is simplified. Furthermore, since it utilizes surface heating by beam irradiation, it is suitable for low-temperature processes, and as a result, it becomes possible to manufacture devices with a high-quality multilayer structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明における平坦化処理の動作原理を説明す
るための図、第2図軸)乃至(e)はそれぞれ本発明に
よる一実施例の工程を説明するための半導体装置断面図
である。 1・・・シリコン基板、 2・・・絶縁膜、 3・・・
ポリV’)1−4、4・・・エネルギービーム、′11
・・・半導体基板、  12.13・・・絶縁膜、  
14・・・配線層、 15・・・層間絶縁膜、  16
・・・平坦化膜(バッファ膜)、  17・・・レーザ
、 25・・・層間絶縁膜、  10・・・一層目素子
、 20・・・二層目素子。 代理人 弁理士  福 士 愛 彦(他2名)第1図
FIG. 1 is a diagram for explaining the operating principle of planarization processing in the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device for explaining the steps of an embodiment of the present invention. . 1... Silicon substrate, 2... Insulating film, 3...
Poly V') 1-4, 4...Energy beam, '11
... Semiconductor substrate, 12.13 ... Insulating film,
14... Wiring layer, 15... Interlayer insulating film, 16
... Flattening film (buffer film), 17 ... Laser, 25 ... Interlayer insulating film, 10 ... First layer element, 20 ... Second layer element. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1

Claims (1)

【特許請求の範囲】 1、デバイス形成後の半導体基板上の凹凸のある表面に
エネルギービーム照射によって選択的に溶融可能な膜を
形成する工程と、 該膜にエネルギービームを照射して溶融させ、該膜の溶
融による流動性により該膜の溶融固化後、半導体表面を
平坦化する工程と、 上層デバイスを形成する工程と を含んでなることを特徴とする半導体装置の製造方法。 2、前記膜は導電膜で構成され、層間の絶縁膜となる下
地絶縁膜の形成後に形成され、更に平坦化後の上記膜上
に上層デバイスを絶縁分離させるための絶縁膜が形成さ
れてなることを特徴とする特許請求の範囲第1項記載の
半導体装置の製造方法。 3、前記膜はポリシリコン導電膜で構成してなることを
特徴とする特許請求の範囲第1項記載の半導体装置の製
造方法。
[Claims] 1. Forming a film that can be selectively melted by irradiating an energy beam on an uneven surface of a semiconductor substrate after device formation; irradiating the film with an energy beam to melt it; A method for manufacturing a semiconductor device, comprising the steps of: planarizing a semiconductor surface after melting and solidifying the film due to fluidity caused by melting the film; and forming an upper layer device. 2. The film is composed of a conductive film, and is formed after the formation of a base insulating film that serves as an interlayer insulating film, and an insulating film for insulating and separating the upper layer devices is further formed on the film after planarization. A method for manufacturing a semiconductor device according to claim 1, characterized in that: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the film is composed of a polysilicon conductive film.
JP14749585A 1985-07-02 1985-07-02 Manufacture of semiconductor device Pending JPS627142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14749585A JPS627142A (en) 1985-07-02 1985-07-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14749585A JPS627142A (en) 1985-07-02 1985-07-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS627142A true JPS627142A (en) 1987-01-14

Family

ID=15431676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14749585A Pending JPS627142A (en) 1985-07-02 1985-07-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS627142A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105937321A (en) * 2016-06-23 2016-09-14 兰州交通大学 Pneumatic stereo garage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105937321A (en) * 2016-06-23 2016-09-14 兰州交通大学 Pneumatic stereo garage

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