JPS6271386A - Video memory - Google Patents

Abstract

PURPOSE:To attain high-speed input/output by transferring optional data in the 1st register to a memory cell array via m sets of transfer means operated by a logical signal by an output signal of a transfer pulse generating circuit and m pieces of data in the 2nd register. CONSTITUTION:Serial data D1 of a digitized video signal in the timing of a clock P1 during the horizontal scanning period is written on the 1st register and bit mask data D2 inputted serially in the timing of the clock P1 is written on the 2nd register. Further, optional row data on the memory cell array 1 in the timing of a clock P4 is read serially. Each data of each bit of the 2nd register 3 and data of the 1st register via a switch gate 12 operated by a AND signal of transfer pulses P2 are transferred selectively simultaneously to an optional row of the memory cell array 1. Then the video signal is inputted/ outputted in real time and the rewrite of the data at each bit or the preservation of the preceding data are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a video memory suitable for delaying or holding a digitized video signal for a predetermined period of time.

[Background of the invention]

Conventionally, a general-purpose dynamic random access memory has been used as a video memory that delays or holds a digitized video signal for a predetermined period of time. This is the February 11, 1985 issue of Nikkei Electronics, published by Nihon Keizai Shimbun.

P232-234. It is described in detail in "Field Memory Using Standard Dynamic RAM". This is because the cost per bit of the dynamic RAM is low, but in order to perform real-time processing of a video signal with a long memory cycle time, parallel processing using memories in parallel is required. However, as the memory capacity per chip increases to 256 bits and 1 Mbit, memory utilization becomes poor when conventional parallel processing techniques are used. Recently, there has been an article published by Nikkei Electronics, published by Nihon Keizai Shimbun, February 11, 1985 issue, pages 219-239゜, titled "Image-only serial input/output type dynamic memory with 520 rows x 700 columns for field memory of TVs and VTRs". As shown in Figure 3, memory has been devised to increase speed by serially inputting and outputting video data. There is a growing demand for video memories that are primarily intended for video signal processing, and that are also easier to use and more versatile.

[Purpose of the invention]

An object of the present invention is to provide a video memory that is capable of high-speed input/output and is suitable for video signal processing.

[Summary of the invention]

An m-bit first register capable of serially inputting data is provided, and the contents of the @1 register are transferred to the memory cell array at once, and the data is transferred from the memory cell array during the period when data is being input to the first register. By reading m bits of data, high-speed data input/output in real time is possible. Furthermore, a second register for m bits into which data is serially input is provided, and the data in the first register is selected using the data in the second register and transferred to the memory cell array, thereby providing a bit mask function. Realize.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention. 1 is a memory cell array with n rows and m columns and a capacity of about 1 field or 1 frame; 2 is a first register into which serial data can be input;
3 is a second register that can also input serial data, 4
selectively transfers data from register 2 to memory cell array 1
5 is a data input terminal to the second register 3, 6 is a data input terminal to the register 2, 7 is a timing and address controller, 8 is a first reference signal input terminal, and 9 is a data input terminal for the second register 3. 2 reference signal input terminals, 10 clock input terminals, 11a to Nm (anto-game), 12a
~12m is a switch gate using a MOS transistor.

1B is an output buffer that serially outputs data (m bits) for one row of the memory cell array 1, and 14 is a data output terminal. Here, the configuration of the memory cell array is such that one row corresponds to one horizontal scanning period of a television signal, and the number of rows is approximately equal to the number of scanning lines.A timing chart is shown in FIG. 2, and the operation will be explained.

In FIG. 2, (1) is digitized video signal data DI input from the input terminal 6, (2) is bit mask data D2 input from the input terminal 5. (
3) is a write clock Ps that takes in the video signal data Dt and the bit mask data D2 into the first register 2 and the second register 3, respectively; (4) fd gives the timing to transfer the data of the register 2 to the memory cell array 1; Transfer pulse p2. (s) is a read clock P that outputs any one row of memory cell array 1 in series.
4. (6) is the read data D3. That is, during the horizontal scanning period (the following three operations are performed).

(Write serial data Dl'jr of the digitized video signal to the first register at the timing of re-clock P1.

(2) Write bit mask data D2 input in series at the timing of clock Pl to the second register.

(5) Serially read data from any one row in the memory cell array 1 at the timing of the clock P4. Next, the following operation is performed during the retrace period. The respective data of each bit of the second register 3 and the transfer pulse P2
The data of the first register is selectively and simultaneously transferred to any one row of the memory cell array 1 via the switch gate 12 which is opened and closed by the product signal (output of the AND gate 11).

In other words, the data in a certain bit of the second register is low (
0), the switch gate becomes 12flOF'F,
The data in the corresponding bit of the register is not transferred, and the corresponding data in memory cell 1 is saved. Conversely, if the data in a certain bit of the second register is high (1), the switch gate 12 is activated during the period O during which the transfer pulse P2 is high.
The corresponding data in the register 8g1 is transferred to the memory cell array 1 and the data is rewritten.

As described above, in this embodiment, when using dynamic memory as the zero memory that can input and output video signals in real time and rewrite data for each pit or store previous data, it is possible to input and output video signals in real time. can be used to perform refresh operations.

One form of the output buffer 15 is to provide an m-bit output register similar to the input section, and transfer data for one arbitrary row from the memory cell array 1 to the output register during the retrace period, and during the scanning period. There is a configuration in which l and t data are read out in series. Alternatively, a static column method, which is well known for general-purpose memories, may be used.

Timing pulses and addressing pulses are generated by a timing & address controller 7. In this case, examples of reference signals input from input terminals 8 to 10 include a vertical synchronization signal, a horizontal synchronization signal, and a clock signal having a frequency that is an integral multiple (usually four times is appropriate) of the color subcarrier frequency of the TV signal. is appropriate. However, this is not limited to lζ.

FIG. 6 shows another embodiment. It is assumed that blocks with the same symbols as in FIG. 1 have the same functions.

The difference from FIG. 1 is that 4 bits of data input are provided in parallel. Therefore, memory cell array 1. 11th/Jista 2. Transfer means 4. Data input terminal 6. The output buffer 15 and the data output terminal 14 each have four thin layers indicated by ad (subscripts) as shown in the figure. However, the second
Register 3, data input terminal 5. Only one timing and address controller 7 is required.

FIG. 4 shows another embodiment. Blocks with the same symbols as in Figure 1 have the same functions. 01A has the number of rows TV
is equal to the number of scanning lines, and the number of columns is 1 in one horizontal period of the TV signal.
The same goes for the memory cell array 1B, IC, and ID which are equal to /4, and it is assumed that 1A to 1·D correspond to approximately one field. For 2A, the number of bits is equal to 1/4 of one horizontal period 1. <
The same applies to the first register 2B into which serial data can be input. 6A is a second register that can input serial data whose number of bits is equal to 1/4 of one horizontal period, and 6B is the same.o4A is a transfer register whose number of bits is equal to the number of bits of the first register. The same applies to 4B.

15, a sense amplifier that reads one memory cell array and any one row of 1B; 16, a memory cell array 1C;
and a sense amplifier that reads out any one row of 1D.

(This timing chart will be shown and the operation will be explained. (1) indicates the time, (2) indicates the data IJ1 input from the input terminal 6. (') indicates the data D1 is input. (4) shows the type of the second register to which the bit mask data input from the input terminal 5 is input, and (5) shows the type of the second register to which the bit mask data input from the input terminal 5 is input. The transfer Hals P2A gives the timing to transfer to 1.

(6) is a transfer pulse P2 that provides the timing to transfer the data of the first V raster 2B to the memory cell array 1.
B, (7) indicates the type of memory cell array to which the data of the first register is transferred, and (8) indicates the operating period of the sense amplifier 15, that is, when any one row of the memory cell array 1A or 1B is connected to the bit line. The period to be read,
(9) indicates the period during which the sense amplifier 16 is operating;
(10) indicates the type of memory cell array 1 from which data is read out in series from the output terminal 14. In period I, the following four operations are performed.

(1) Data D1 and D2 from data input terminals 6 and 5 are written to the first register 2A and second register 3A, respectively.

(2) Of the data in the second register 2B, data that is not masked by the contents of the second register 3B is transferred and written to an arbitrary row of the memory cells 1D.

(3) An arbitrary row in one memory cell array reproduced by the sense amplifier 15 is read out from the serial output terminal 14.

After the operation in (2) is completed, the sense amplifier 16 starts reading an arbitrary row of the memory cell array 1C in preparation for reading in the period π.

During the period ■, the following four operations are performed.

(1) Data DIrD2 from data input terminals 6 and 5 are written to the first register 2B and second register 6BI, respectively.

(2)! Of the data in the register 2A, the second register 3
The unmasked data of the contents of A is transferred to an arbitrary row of the memory cells 1A.

(6) An arbitrary row in the memory cell array 1C reproduced by the sense amplifier 16 is read out from the output terminal 14 in series.

(4) (2: After the operation of ' is completed, the sense amplifier 15 starts reading an arbitrary row in the memory cell array 1B.

As can be easily inferred from the same figure, similar operations are repeated during periods I to ■. In this way, data for the retrace period will be written.

Can be held and delayed. In the example of FIG. 4, since there is a period in which one of the sense amplifiers 15 and 16 is not operating, it is possible to use this period as a refresh operation period for the memory cells. Therefore, it is suitable for reading out the output using a static column method.

Although FIG. 4 shows data input using one bit, it can be easily inferred that multi-bit input is possible as in the embodiment shown in FIG.

The number of bits in the first register 2 and the second register B is equal to the horizontal scanning period in the example of FIG. 1, and is equal to one horizontal period in the example of FIG. The number of bits is not limited to these two examples.

FIG. 6 shows a specific circuit for realizing the embodiment shown in FIG. MOS transistor 7 shown for arbitrary 1 bit
, and inverter 8.19 constitute, for example, a pit register 60 indicating an arbitrary bit of the second register 6 in FIG.

MOS transistor 21.22. and inverter 25
．． At 24, for example, a pit register 61 indicating an arbitrary bit of the register shown in FIG. 1 is constructed. NOR circuit 2
0 and MOS transistor 25°26, for example, the first
It constitutes any one of the transfer means 4' in the figure. One MOS transistor 27t 29 (indicated by broken line 62)
．． 31+ b5 and one capacitor 2B, 50.52
．． 34 combinations, each with 1 bit memory cell (2
7,28), (29,3o).

(31, 32) and (33, 34) are constructed. Inverter 35, 36 and MOS transistor 57 constitute a sense amplifier (indicated by broken line 63) 38, 59
is a MO3I-transistor. 40 is, for example, the first
41 is an input terminal for a pit selection signal of the second register 2, 42 is a data input terminal of the second register, and 46 is an input terminal for a pit selection signal of the second register 3 in the figure. a transfer pulse input terminal that provides timing for transferring data to the memory cell array 1;
44 is an inverter. 45c is a data input terminal of the 1st register; 46 is an inverter. 47 to 50 are arbitrary four word lines. Reference numeral 51 denotes a sense amplifier control signal line, and this control signal controls the operating state and non-operating state jll of the sense amplifier 65. Specifically, the non-operating state means, for example, that the inverter 35. ')6
By turning off the power supply to the inverter 55.3, etc.
If the input/output part of 6 is placed in a floating state. 52 is a control signal line for opening and closing MOS transistor S7, 55.54 is a pair of pit lines, 5
5゜56 is a pair of data output lines, 57 is an output bit selection signal input terminal, and 58 is a single pair of output signals (7
) A buffer that converts to a thick level signal and outputs it.
59 is a data output terminal. Next, a timing chart is shown in FIG. 7, and the operation in FIG. 6 will be explained. (a) is a bit selection signal input from the input terminal 40, (b)
is the data input from the input terminal 42, (C) is the bit selection signal input from the input terminal 41, (d) is the data input from the input terminal 45, and (e) is the output of the pit register 60. .

(f) H, output side data of pit register 61 (-output side data of pit register 61, (g) MOS transistor 5
The signal (h) of the control signal line 52 that opens and closes 7 is 1
The potential of the paired bit lines 53 and 54, (i) is the input terminal 4
3, the transfer pulse that gives the timing to transfer the data of @registor to the memory cell array, (j) is the output of the NOR circuit 2D, Qc) the selection signal of the food line 47, (1) is the sense amplifier 63 At the timing of the bit selection signal inputted from the input terminal 40 at time n 1+, which is the signal of the control signal line 51 to be activated,
The data input serially from the input terminal 42 is latched into the bit register 60 of the second register. At this time, the output of the bit register 60 is inverted in this example and becomes a low level. Similarly, data serially input from the input terminal 45 is latched into the pit register 61 of the first register at the timing of the bit selection signal input from the input terminal 41. At this time, the output of the pit register 61 is ``1'' on the output side of the inverter 23, and ``low'' on the output side of the inverter 24. With the above operation, data is latched into any pin of the second register or register. Next, the operation of transferring the data of the first register to the memory cell array will be explained. At time t2, a high level signal is input from the input terminal 52, the MOS transistor 57 is turned on, and the bit lines 53 and 54 are shorted.

A pair of bits just before a short circuit! 53.54 is high on one side,
Bit line 53 after short circuit because the other one is low
．． The potential of 54 is approximately 1/2 of the power supply voltage. next,
When a transfer pulse is input from the input terminal 43 at time t3 to provide timing for transferring the data of the first register to the memory cell array, the output of the NOR circuit 20 becomes high, the MOS transistors 25 and 26 are turned on, and the pit register 61 is turned on. The contents of are output to a pair of bit lines 55 and 54.

At almost the same timing as the transfer pulse, an arbitrary word line (here, the word line 47) becomes NO, and the memory capacitor 28 is selected. At time t4, a control signal for the sense amplifier 63 is input, and the sense amplifier 6
3 becomes active and amplifies the potential difference between the bit lines 53 and 54, fixing the bit line 53 to high and the bit line 54 to low. This is v'r of MOS transistor 25.26.
This is even more effective when the Z line 56 does not rise to the power supply voltage in the H situation. Thereafter, the word line 47 becomes low at time t5, and writing of data to the capacitor 28 is completed. The above description is based on the case where high data from the input terminal 42 is latched into the pit register 60 of the second register, and then low data from the input terminal 42 is latched.

FIG. 8 shows a timing chart in this case. (a
) is the control signal of the control signal line 52 that opens and closes the MOS transistor 37, (b) is the potential of the bit line 55.54, (C) is the selection signal of the word line 47, and (d) is the signal that operates the sense amplifier 65. This is the signal on the control signal line 51 that sets the state.

In this case, the output of the bit register 60 will be high, so
The output of NOR circuit 20 is always low.

Therefore, MOS transistors 25, 261r! Always off. The period from time t2 to t4 is the same as the previous explanation. At time t3, word line 47 goes high.

Here, if a high level is written to the capacitor 2, the potential of bit i153 will rise slightly, and a slight potential difference will occur between bit lines 55 and 54. This potential difference is determined by the relationship between the capacitance value of the capacitor 28 and the parasitic capacitance and stray capacitance of the bit line 55. At time t4, when the sense amplifier control signal line 51 goes high and the sense amplifier 63 becomes operational, bit 11
At time 0 ts, when the potential difference between 153 and 54 is amplified, the bit line 53 becomes high and the bit line 54 becomes low, the word line 47 becomes low and the original data is held in the capacitor 28. Furthermore, if a low level is written to the capacitor 28, if the word line 47 becomes NO at time t3, the bit line 53 will drop slightly, and the bit line 53, 54
The slight potential difference between the open circuits is amplified by the sense amplifier 63, and the capacitor 28 is held at a low level at the timing when the word line 47 goes low. As mentioned above,
By latching into any pit register 60 of the second register, it is possible to control whether or not the contents of the corresponding pit register 62 of the second register are transferred to the memory cell array according to the data contents. The signal timing is an example, and the phase, Nockles width, etc. are not limited to this figure. (9) The bit selection signals inputted from the input terminals 40 and 41 may be exactly the same, so they can be shared.

In Figure 1, they are common.

Next) The read operation will be explained. A timing chart is shown in FIG. (a) is MOS transistor 5
(b) j
t, the potential of the bit lines 53 and 54, (C) the potential of the word line 4
7, (d) is the signal on the control signal line 51 that controls the sense amplifier 65, (e) is the signal on the input terminal 5.
The read bit selection signal input from 7, (f) is
The potential of output lines 55 and 56 is shown.

At time tl, control signal line 52 goes high and bit lines 53,54 are shorted. Word line 4 at time t2
7 goes high and the data on capacitor 28 is transferred to bit line 5.
5. Here, if the capacitor 28 is held at a high level, the potential of the bit line 53 rises slightly, and a potential difference is generated between the bit lines 53 and 54. At time t3, the control signal line 51 goes high, the sense amplifier 63 becomes operational, and the bit line 55
．． The potential difference between the bit lines 54 and 54 is amplified, and the bit line 53 becomes high and the bit line 54 becomes low. At time t4, word line 47 goes low, and capacitor 28 retains the original data. At time ts, a read bit selection signal is input from the input terminal 57, and the MOS transistor 38.59 outputs the data on the bit line 55.54 to the output line 55.
．． 56 respectively. Output line 55 before t5
．． The potential of 56 has a value determined by the information of the bit read immediately before, but is not related to the reading of that bit. The data on output lines 55 and 56 is converted to a single logic level by buffer 58 and output from output terminal 59.

Another embodiment is shown in Figure 10. Similar to FIG. 6, FIG. 10 illustrates a corresponding arbitrary bit of the second register, register, and transfer means. However, memory cells, sense amplifiers, output lines, etc. are not shown. 6
4f′i capacitor.

65 is an AND circuit. Elements, blocks, and lines with the same symbols as in FIG. 6 have the same functions. The difference from FIG. 6 is that any bit register 6 of the second register
0 is constructed from a MOS transistor 17 and a capacitor 64. In this configuration, if a boost signal (for example, 7V) is used as the bit selection signal input from the input terminal 40, the influence of the VTH of the MOS transistor 17 can be suppressed. The operations of other blocks are basically the same as in Figure @6.

FIG. 11 shows the main part of yet another embodiment of the present invention. In the figure, 66a to 66m are switches, respectively, which switch between a positive phase output and an inverted output of each bit output of the second register 3. Reference numeral 67 is an input terminal for a control signal for controlling the switches 66a to 66m. Components with the same numbers as in FIGS. 1 and 4 have the same functions. The feature of the embodiment shown in FIG. 11 is that it is possible to obtain the same effect as instantaneously inverting the contents of the second register 5 by means of a control signal inputted from the input terminal 67. The operation of the embodiment shown in FIG. 11 will be explained using FIG. 12. In FIG. 12, the same numbers as in FIG. 1 and FIG. 11 have the same functions. In FIG. 12(n), the data of video signals A and B are input to the 8g register 2, and the data is input to the second register 3 so that the information of the video signal A can be selectively written into the memory cell array 1. ing. Next, in FIG. 2B, the information in the second register 2 is written into the memory cell array 1. At this time, the input terminal 6 is connected so that only the information of the video signal A can be written into the memory cell array 1, corresponding to the ± data stored in the second register 3.
A control signal is added to the input terminal 67 in advance (1).Next, in FIG. 7C, the control signal at the input terminal 67 is inverted, and only the information of the video signal B can be written into the memory cell array 1 this time. It can be easily understood that if the row selection address of the memory cell array is changed in advance at this time, the video signals A and B can be successively written to different rows, as shown in (c). The functions shown in FIG. 12 in the embodiment of FIG. 11 are very effective in applications where, for example, a television screen is vertically divided to display video signals A' and B, respectively.

When writing video signals whose synchronization phases do not match each other to a video memory that performs serial read-in and read-out, use a field memory or frame memory and a frame synchronizer.
The main video signal (the video memory and display system operate in synchronization with this video signal) is synchronized with the sub video signal (this video signal has a synchronization signal that does not match the operation of the display system and video memory). ) must be matched. However, in the configuration shown in FIG. 11, only horizontal synchronization needs to be adjusted, and horizontal synchronization phase adjustment can be realized with one or two line memories.

In addition, in the embodiment shown in FIG.
It goes without saying that if the lucky number is fixed, it is possible to operate exactly the same as the embodiments shown in Figures M1 to 10.

Another embodiment of the present invention is shown in FIG. FIG. 13 shows a corresponding arbitrary bit of the first register, second register, and transfer means. Memory cells, sense amplifiers, output lines, etc. are not shown. In the same figure,
68 and 69 are inverters, 70 to 77 are transfer gates, and the elements, lines, and lines having the same symbols as in FIG.
It is assumed that the blocks have the same function. In this embodiment, the writing force ζ input terminal 4 to the second register 60
The transfer means 62 is constructed by serially connecting transfer gates 74 and 76 or 75 and 77 as shown in FIG. 6 or @10. This is different from the example in the figure. It also functions as a switch for switching the output of the second register 60 in response to control signals from the inverter 69, transfer gates 72 and 731fi, and input terminal 67.

This corresponds to the switches 66a to 66m in FIG. 11, and it can be easily inferred that this embodiment can operate as shown in FIG. 12.

FIG. 14 shows yet another embodiment of the present invention. FIG. 14 illustrates the corresponding arbitrary bit of the first register, second register, and transfer means. In the same figure, 7
8 is a PMOS transfer gate, which corresponds to the transfer gate 73 in FIG. Also, 79.80 is NOR game 1-. 81.82 is an AND gate.

In Fig. 14, parts with the same symbols as in Fig. g15 have the same functions. FIG. 14 shows that any bit 60 of the second register consists of N' OR gates 79 and 80;
A large number of transfer gates are used for saving control, AND
The configuration is the same as that of FIG. 16, except that the gates 81 and 82 are used, and the inverter 69 is sluggish because the transfer gate 78 is PMO3, and the same operation can be performed.

FIG. 15 ζζ shows yet another embodiment of the present invention. FIG. 15 II, the second register, the second register and the transfer means 2
” is illustrated for an arbitrary bit corresponding to llf
In the f1 diagram, 85 is an exclusive OR gate, 8
4 and 85 tristate buffers. 15th
In the figure, elements, blocks, etc. with the same symbols as in FIGS. 6 and 10 have the same functions. In this embodiment, the exclusive 0R838 is used instead of selecting the output of the second register 60. The difference from FIG. 15 is that a tri-state counter 7784.85 is used as a means for transmitting the output of the second register 61 to the bit line 53.54, but each input terminal receives a control signal at the same timing. It can be easily inferred that it is possible to input data and perform the same operation.

FIG. 16 shows another embodiment. It is assumed that blocks with the same symbols as in FIG. 1 have the same functions.

A third register 86 latches all the data in the second register 2 with the same transfer timing, and has the same number of bits as the second register 2 (m bits). 87 is a fourth register that latches all the data in the 1g2 register 3 at the same transfer timing, and the number of bits is also m bits. 88 is an output register that latches consecutive m bits of data in the memory cell array 1 at the same transfer timing & 89 is an output $
This is a second output register that latches data from the register 88 at the same transfer timing and outputs the data in series. The memory cell array 1 has a structure in which the number of two columns is an integral multiple of the number of bits In of the register 2, and the a capacity is approximately one field. It is assumed that P3, the output of the timing address controller 7, selects 10 rows of the memory cell array, and Pa selects columns in units of m bits. P7 is memory cell array 1
Pa is a pulse that provides the timing to transfer the data of the continuous m bits to the output register 88, and Pa is a pulse that provides the timing to transfer the data of the output register 88 to the second output register 89.

FIG. 17 shows a timing chart and the operation will be explained.

In FIG. 17, (1> is the input data from the input terminal 6 to the second register 2, (2) is the input data from the input terminal 5 to the second register 3, +31°+4), +5),
+6), (7) and (8) are the outputs P1.+6), (7) and (8) from the timing table address controller 7, respectively. P5゜P2.
P7. Ps, P4. (9) is the output second register 8
This is output data D5 from 9.

During period 1, the following five operations are performed at the timing shown in FIG.

1) Data D1 input from input terminal 6 is pulse P1
Continuous m-bit data is stored in the register 2 at the timing of pulse P5, and all m-bit data of the register 2 is transferred to the sixth register 86 at the timing of the pulse P5.

2) Data D2 input manually from input terminal 5 becomes pulse P1
At the timing of pulse P5, consecutive m bits of data are taken into the 42 register 3, and at the timing of the pulse P5, all m bits of data in the stripe 2 register 5 are transferred to the 44 register 87.

5) At the timing of pulse P8, all m-bit data of the second output register 88 is transferred to the output %2 register 89, and the pulse ? At timing 4, n-bit data is serially output.

4) Transfer m consecutive bits of data in the memory cell array 1 specified by the row selection signal P6 and column selection signal P6 to the output register 88 at the timing of the pulse P7.

5) At the timing of pulse P2, m of the third register 86
Among the bit data, the data in the fourth register 87 is the data that was not masked.

Row selection signal P3. The data is transferred to the area in memory cell array 1 specified by column selection signal P6.

The same operation is performed for the period 12 Kanpaku.

In the above explanation, it was explained that the data D1 from the input terminal 6 is serially taken into the g register 2 for m pits and transferred to the 43 register 86 at the timing of the pulse P5.
The timing explained below may also be suitable.

4 Load (m-1) bits of data into register 2 1
The next m-th bit data has already been taken in (+n-
1) Directly transfer to the 45 register 86 at the same timing as the bit data.

In this case, the number of bits of the four registers 2 can be reduced by one bit. This operation can also be applied to transfer from the second register 3 to the fourth register 87. Also output No. 11/
It can be easily inferred that the same applies to the transfer from the register 88 to the second output register 89. moreover,
Although FIG. 16 has been explained using a one-pict input, it is clear that a multi-bit input may also be used, as in the examples of FIGS. 1 and 3.

FIG. 18 shows an embodiment of the present invention. In this example, the number of 10 columns of the memory cell array is N times the number of bits m of the second runster (
(N is an integer), from the input section to the output section corresponding to 201 bits of the register. However, in this example.

Two memory cells are shown on one bit bear.

Other cells are omitted. It is assumed that block elements having the same reference numerals as in FIGS. 6 and 14 have the same functions. 91 is the 2nd Lujista. The data in the second register 6 is
Register 86. Signal lines 92.95 and 94.95 of signal P5 that provides timing for transfer to fourth register 87
is a MOS transistor and has the function of a transformer 77 gate. 96.97 is an inverter, and 96.97 constitutes a latch for 8701 bits of the fourth register. 98
．． 99 is the inverter, 98.99 is the fifth register 86
Configures a 01-bit latch. 100A~100N
'11O5) Run/Star, 111IA~101N
is a capacitor; a MOS transistor 100 and a capacitor 101 constitute a 1-bit memory cell in the memory cell array 1. 102A-102N are MOS transistors, 105A-105N are ri capacitors. MOS transistor 1u2.

MOS) U/Dimeta 100 and capacitor 103 have the same function as capacitor 101. 105A1-105
) 12 is a MOS transistor.) It has the function of a transformer 77 gates. 106AI and 106A2 are a pair of bit lines.

The same applies to 106B1 and 106B2 to 106N1 and 106N2.

1048 to 104N are any 1 of 5g3 register 86
Bit 7 output line (i'N1 fixed bit line pair 106
This is a signal line for selecting which one of 8 to 1116N to connect to. This can be obtained by decoding the column address data. This allows m bits 4Lfi in column direction)
Also, 2 nodam access is 0 chono.

107v'i A signal line for a signal P7 that provides timing for transferring continuous m1-specific data in the memory cell array 1 to the first output register 88; 108 and 109 are M
OS Transoster has the function of Trans7 Agate. 11 [! , 110,1 with 111 rt inverter
11 constitutes a latch for one bit of the second output register 68. Reference numeral 112 denotes a signal line for a pulse P8 which provides timing for transferring the data of the output 5g register 88 to the second output register S9. IC5 and 114 are MOB transistors having the function of a transformer 77 gate. 115,
Reference numeral 116 indicates eleven inverters, and 116 constitutes a latch for one bit of the second output register 89.

117 and 11d are inverters having a buffer function.

119 and 120 are MOf3) transistors which have the function of a transfer gate. 121 and 122 are output line bears.

,,G In the configuration shown in Figure 18, the number of 60 bits in the register 22g2 is 4, so the second
It is easy to arrange the register 2 and the second register 5 in parallel on the IC soyout.

In FIG. 18, Lujista 2. Although the second register 6° output second register 89 is shown as a data selector type latch, C1T- may also be configured as a shift register.

In the present invention, an m-bit register for manually inputting serial data and an m-bit 42-7 register for inputting serial data are installed, and one transmission pulse is connected to each of the m-bit data in the second register. Among the m-bit data in the second register, arbitrary data corresponding to the data in the second register is transferred to the memory cell array through the transfer means operated by the logic signal. This makes the bit mask function zero.

In addition, since the input data is taken into the second register 1 of 2m bits, high-speed input is possible, and the period of time when data is taken into the second register is short! Since writing does not monopolize the memory cell array all the time, reading can be performed at high speed.

Margins below [Effects of the Invention] According to the present invention, it is possible to realize a video memory that can input and output digitized video signals in real time and that can perform a bit-by-bit masking function.

[Brief explanation of drawings]

@ Figure 1 is a configuration diagram of an embodiment of the present invention, and Figure 2 is a timing chart 1 for explaining Figure 1. 3 is a block diagram of another embodiment of the present invention, FIG. 4 is a block diagram of still another embodiment of the present invention, FIG. 5 is a timing chart for explaining FIG. 4, and FIG. 6 is a block diagram of another embodiment of the present invention. is a configuration diagram of still another embodiment of the present invention,
7, 8, and 9 are timing charts for explaining the embodiment shown in FIG. 6, FIG. 10 is a configuration diagram of still another embodiment of the present invention, and FIG. 11 is a timing chart for explaining the embodiment of the present invention. FIG. 13 is a schematic diagram for explaining the operation of the embodiment shown in FIG. 11, and FIG. 12 is a block diagram of another embodiment. FIG. 14 and FIG. 15 are block diagrams of still other embodiments of the present invention. 422=l Nimo Isamu - 5g Figure 16 is a configuration diagram showing an embodiment of the present invention, and Figure 17 is a timing chart of the practical example shown in Figure 17. FIG. 1e1 is a block diagram of another embodiment of the present invention. 1. Memory cell array 2. Second register 5.
...Second register 4...Transfer means 7...
Timing address controller 14...output buffer

Claims (1)

[Claims] It has a memory cell array, an m-bit first register into which serial data can be input, an m-bit second register into which serial data can be input, and a transfer pulse generation circuit, and the output signal of the transfer pulse generation circuit and Any data in the first register is transferred to the memory cell array through m transfer means that operate on logic signals with m respective data in the second register. video memory.