JPS6266665A - Manufacture of driving circuit substrate - Google Patents
Manufacture of driving circuit substrateInfo
- Publication number
- JPS6266665A JPS6266665A JP60205306A JP20530685A JPS6266665A JP S6266665 A JPS6266665 A JP S6266665A JP 60205306 A JP60205306 A JP 60205306A JP 20530685 A JP20530685 A JP 20530685A JP S6266665 A JPS6266665 A JP S6266665A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating film
- forming
- film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims abstract description 45
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 23
- 239000011159 matrix material Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 241000282485 Vulpes vulpes Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000011002 quantification Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分計〕
本発明は薄膜スイッチング素子をマトリックス状に配列
してなる表示装置の駆動回路基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Summary of the Invention] The present invention relates to a method for manufacturing a drive circuit board for a display device in which thin film switching elements are arranged in a matrix.
〔発明の技術的背景とその間1点〕
エレクトロルミネッセンスパネル、発光ダイオード、プ
ラズマパネル、螢光表示管、液晶パネルなどの表示デバ
イスは、表示部の薄型化が可能であシ計測機器、事務機
器やコノピユータ等の端末表示装置fあるいは特殊な表
示装置への用途として要求が強t−>ている。これらの
中で薄膜トランジスタを用いたエレクトロルミネッセン
スや液晶表示装置は、低消費電力化や低コスト化が可能
であるために表示デバイスとして注目され、近年各所で
開発されティる(例えばIEEE Trar、5act
ion onElectron Device M
ol ED−20,No・11.November1
973・PP995−1001参照)。このようなスイ
ッチングトランジスタの材料としては結晶、多結晶、ア
モA/ 77 X状態ノ8i或いはCd8e、 Te、
Cd8等が用いられている。この中でも多結晶半導体
やアモルファス半導体を用いた薄膜素子は、低温プロセ
スが可能な九めにガラス基板等の比較的低温で取扱うこ
との必要な基板上にもスイッチングトランジスタ等のア
クティブマトリックス素子゛を形成することができ、低
価格で大面積の表示装置を実用段階にした。[Technical background of the invention and one point] Display devices such as electroluminescent panels, light emitting diodes, plasma panels, fluorescent display tubes, and liquid crystal panels can have thinner display parts, and are used in measuring instruments, office equipment, and other devices. There is a strong demand for use in terminal display devices such as computer computers or special display devices. Among these, electroluminescence and liquid crystal display devices using thin film transistors have attracted attention as display devices because they can reduce power consumption and cost, and have been developed in various places in recent years (for example, IEEE Trar, 5act
ion on Electron Device M
ol ED-20, No. 11. November1
973, PP995-1001). Materials for such switching transistors include crystal, polycrystal, AmoA/77X state No.8i or Cd8e, Te,
Cd8 etc. are used. Among these, thin film devices using polycrystalline semiconductors or amorphous semiconductors are capable of low-temperature processing, and active matrix devices such as switching transistors can also be formed on substrates that need to be handled at relatively low temperatures, such as glass substrates. This has brought a low-cost, large-area display device to the practical stage.
@4図は一般的な薄膜トランジスタを用いた表示装置の
等価回路である。アドレス配、f) (11) (11
1−112、113・・・・・lln )は横方向に並
ぶ薄膜トランジスタ(13)のゲート電極をドライブし
、データ配線(12) (121、122、123・1
1 @ @ @ 12m )は縦方向に並ぶ#IIJ)
う/ジスタ(13)のソース′c電極に画像信号を与え
る。薄膜トランジスタ(13)の各々はアドレス配41
1(11)とデータ配GN(12)の各交点に対応した
画素毎に設けられ、各ドレイン□1を極は表示素子(1
5)と共にキャパシタ(14)にも接続されている。Figure @4 is an equivalent circuit of a display device using a general thin film transistor. Address distribution, f) (11) (11
1-112, 113...lln) drive the gate electrodes of the thin film transistors (13) arranged in the horizontal direction, and the data wirings (12) (121, 122, 123, 1
1 @ @ @ 12m) are #IIJ arranged vertically)
An image signal is applied to the source 'c electrode of the image register (13). Each of the thin film transistors (13) has an address wiring 41
1 (11) and the data distribution GN (12), and the pole of each drain □1 is connected to the display element (1
5) and is also connected to a capacitor (14).
表示素子(15)は、例えば液晶である。具体的に液晶
表示装置を例にとると、アドレス配線(11)、データ
配線(12)、 )ランジスタ(13)およびキャパ
シタ(14)を集積形成し九駆動回路基板とこれに対向
する透明電極を全面に形成しfc基板との間に液晶層を
挟持することによシ構成される。また最近ではここで使
われている薄膜トランジスタのON −0FF特性等が
改善され補助容量となるキャパシタ(14)がなくても
実質的には表示装置(15)となる液晶自体のもつ容量
だけで“コ込んだ画像情報黛の保持タイムを充分長くと
れるようになっに0すなわちアクティブ・マトリックス
型の表示装置は、アドレス配線の走置毎に−ライフ分の
画1膚データをJ込む線順次定量方式の採用により表示
素子(15)をデユーティ比をほぼ100%で駆動する
ことができるために見易い画像が得られるもので套る。The display element (15) is, for example, a liquid crystal. Taking a liquid crystal display device as an example, an address wiring (11), a data wiring (12), a transistor (13), and a capacitor (14) are integrally formed, and nine driving circuit boards and transparent electrodes facing the same are formed. It is constructed by forming it on the entire surface and sandwiching a liquid crystal layer between it and the FC substrate. In addition, recently, the ON-0FF characteristics of the thin film transistors used here have been improved, and even if there is no capacitor (14) serving as an auxiliary capacitance, the capacitance of the liquid crystal itself, which serves as the display device (15), is sufficient. The active matrix type display device is now able to retain the stored image information for a sufficiently long time, and is based on a line-sequential quantification method in which one life's worth of image data is stored for each address wiring run. By adopting this, the display element (15) can be driven at a duty ratio of approximately 100%, so that an easy-to-see image can be obtained.
ところでこの櫨のディスプレイパネルは近年。By the way, this oak display panel is made in recent years.
大面積で高精細化へと進んで2す、これらの大容f型ア
クティブマトリックス基板の実現、あるいは大面積表示
で実現するには、トランジスタの数が非常に多くなる。As we move toward larger areas and higher definition2, the number of transistors will be extremely large in order to realize these large-capacity F-type active matrix substrates or large-area displays.
例えば、アドレス1500xデータ20000時であれ
ば3000000素子が必要であり、アドレス配線とデ
ータ配線との交点の数やキャパシタの数もそれぞれ30
00000個必要となる。For example, if the address is 1,500 x the data is 20,000, 3,000,000 elements are required, and the number of intersections between address wiring and data wiring and the number of capacitors are also 30 each.
00000 pieces are required.
このような大規模のトランジスタアレイをもつ駆動回路
基板を歩留り良く製造することは非常に困難なものとな
る。これらの欠陥の主原因としては(1)多層配線間あ
るいはキャパシタの電気的短絡、(2)配線の断線、(
3)トランジスタの欠陥等が考えられる。しかし、ディ
スプレイパネルの点欠陥がある程度ゆるされるならば配
線の断線やトランジスタの欠陥は余り大きな問題とはな
らない。例えば第 図において、アドレス配線(11)
がその途中の一点で切断されてもアドレス配線(11)
の両方向から信号を入れるととくより、他の画素にはま
りtく動作上影響を及ぼさないし、又、切断の位置によ
ってはすべての画素が正常に動作することが期待される
からである。It is extremely difficult to manufacture a drive circuit board having such a large-scale transistor array with a high yield. The main causes of these defects are (1) electrical short circuits between multilayer interconnects or capacitors, (2) disconnections in interconnects, (
3) There may be a defect in the transistor, etc. However, if point defects in the display panel can be tolerated to some extent, disconnections in wiring and defects in transistors will not be a big problem. For example, in Figure 1, address wiring (11)
Even if the address wiring is cut at one point along the way (11)
This is because inputting signals from both directions does not affect the operation of other pixels, and it is expected that all pixels will operate normally depending on the position of the cut.
これに対し、多層配線間の短絡は点欠陥では済まないか
ら、ディスプレイパネルにとって大きな影響を与える。On the other hand, a short circuit between multilayer interconnections is not just a point defect, and has a significant impact on the display panel.
しかも、短絡位置をレーザー等で分離することは可能で
おるが、そのためには短絡位置を知る必要があり、これ
は断線チェックと異なし検査に膨大な時間がかかる。更
に短絡箇所の分離を行う工程も増えるため、生産性が低
下することはさけられない。このように短絡欠陥は眉間
絶縁膜が結晶シリコンの熱酸化膜と異なり、低温でスパ
ッタ法やCVD法で形成しなくてはならず。Moreover, although it is possible to separate the short circuit position using a laser or the like, it is necessary to know the short circuit position, which requires a huge amount of time to check for disconnection and inspect for differences. Furthermore, since the number of steps for separating short-circuited parts is increased, productivity is unavoidably lowered. In this way, short-circuit defects occur because the glabella insulating film is different from a thermally oxidized film of crystalline silicon and must be formed at low temperatures by sputtering or CVD.
その膜質が非常に劣ることが起因しており、特に、ディ
スプレイパネルの大面積化に伴ってかなりの数になるこ
とが予想される。又、これらの欠陥をなくすために、層
間絶縁膜を陽極酸化法で形成することも試みられている
。しかし、陽極酸化法のみで作られる酸化膜を用いてト
ランジスタを形成することは特性上バラツキが非常に多
くなるなどの問題があっ九〇
〔発明の目的〕
この発明は上述した従来の間趙点を解決し、多層配線の
jiJ間短絡を効果的に防止してディスプレイパネルの
歩留向上、信頼性向上を図り得る駆動回路基板の製造方
法を礎供するものでちる。This is due to the very poor quality of the film, and it is expected that the number will increase considerably as display panels become larger in area. Furthermore, in order to eliminate these defects, attempts have been made to form an interlayer insulating film by an anodic oxidation method. However, forming a transistor using an oxide film made only by the anodic oxidation method has problems such as large variations in characteristics. The present invention provides a method for manufacturing a drive circuit board that can solve the problems and effectively prevent short circuits between ji and j in multilayer wiring, thereby improving the yield and reliability of display panels.
すなわち本発明は、まず絶縁性基板上に第1の導電体層
と第1の絶縁膜を順次付着し、欠いでこの、Jlの絶縁
膜に加工を施して所望のパターンを作る。このあと表面
に露出した第1の導電体層を酸化せしめて第2の絶縁膜
とするとともに、第1の絶縁膜パターンで被覆された第
1の導電体層からアドレス配線どゲート電極を作り出す
。スと透明導電膜を用いた画素″を極と、ゲート電極上
の領域T/cあって第1の絶縁膜上および第2の絶縁膜
上に一部が重なる半導体薄膜パター7を形成する。That is, in the present invention, first, a first conductor layer and a first insulating film are sequentially deposited on an insulating substrate, and then the Jl insulating film is processed to form a desired pattern. Thereafter, the first conductive layer exposed on the surface is oxidized to form a second insulating film, and address wiring and gate electrodes are created from the first conductive layer covered with the first insulating film pattern. A semiconductor thin film pattern 7 is formed with the pixel '' using a transparent conductive film as a pole, a region T/c on the gate electrode, and partially overlapping the first insulating film and the second insulating film.
そうして次に、アドレス配線と直交するデータ配線と、
このデータ配線の所望の箇所より延教され半導体薄膜パ
ター7の一部へ重なゐノースジ極と、一方でこの半導体
薄膜パターンに接続をなし他方で画素電極と接続をなす
ドレイン電極を形成することにより駆動回路基板を得る
ことができる。Then, the data wiring perpendicular to the address wiring,
A north pole extending from a desired location of this data wiring and overlapping a part of the semiconductor thin film pattern 7, and a drain electrode connected to this semiconductor thin film pattern on the one hand and the pixel electrode on the other hand are formed. A drive circuit board can be obtained.
本発明によれば第1の絶縁膜にピノホールが存在してい
ても、このピンホールで露出した第1の導電体層が第2
の絶縁膜となる九めに、多層配線構造を持つマ) IJ
フックス線の眉間短絡欠陥を未然に防ぐことが出来る。According to the present invention, even if pinholes exist in the first insulating film, the first conductive layer exposed by the pinholes is
IJ has a multilayer wiring structure and serves as an insulating film.
It is possible to prevent the glabella short circuit defect of the Fuchs wire.
この九めディスプレイパネルの歩留向上、信頼性向上を
図ることができる。It is possible to improve the yield and reliability of this ninth display panel.
第1図(a)〜(15)は本発明の製造工程を示す平面
図。FIGS. 1(a) to (15) are plan views showing the manufacturing process of the present invention.
また第2図は本発明の製造方法によって得られた表示装
置用駆動回路基板の断面図を示す。以下本発明の一実施
例を第1図(al〜(eli?よび第2図を併用して説
明する。Further, FIG. 2 shows a cross-sectional view of a display device drive circuit board obtained by the manufacturing method of the present invention. An embodiment of the present invention will be described below with reference to FIGS.
先ず、例えばガラス板等の透明な絶縁性基板(1)上に
厚さ約20001のTa膜からなる第1の導電体1?!
(2)をスパッタリング法により蒸着する。次に例えば
プラズマ、光、マイクロ波、熱等を利用したCVD法あ
るいはスパッタリング法により、約200OAのシリコ
ン酸化g (8i02 )からなる第1の絶縁膜(3)
を付着する。次に所望のホトレジストパターンを形成し
て第1の絶dd(3)にエツチング加工を施す。しかる
のち、このホトレジストを除去し、例えばホウ酸系の溶
telを用いて第1の、sm膜(3)のパターンで覆わ
れていない第1の導電体層(2)を表面から絶縁性基板
(1)面に至るまで陽tfj市化を施こし第2の絶縁1
11(4)とすれば、第1の絶縁膜(3)のパターンで
覆われたところの第1の導電体層はアドレス配線(2−
1)とゲート1極(2−2)とこのアドレス配!(2−
1)の基板周辺における配線パッド(2−3)が作られ
るC図1 (a) )。First, a first conductor 1 made of a Ta film with a thickness of about 20,000 mm is placed on a transparent insulating substrate (1) such as a glass plate. !
(2) is deposited by sputtering. Next, a first insulating film (3) made of approximately 200 OA of silicon oxide g (8i02) is formed by, for example, a CVD method or a sputtering method using plasma, light, microwaves, heat, etc.
Attach. Next, a desired photoresist pattern is formed and the first resist dd (3) is etched. After that, this photoresist is removed, and the first conductive layer (2) not covered with the pattern of the first SM film (3) is removed from the surface of the insulating substrate using, for example, a boric acid-based molten tel. (1) Apply positive TFJ up to the surface and apply the second insulation 1
11(4), the first conductor layer covered with the pattern of the first insulating film (3) is the address wiring (2-
1), gate 1 pole (2-2) and this address arrangement! (2-
Figure 1 (a)) where wiring pads (2-3) around the substrate in 1) are made.
次に新たなホトレジストを形成し、配線パッド(2−3
)上の第1の絶縁膜(3)のエツチング加工し所定の大
きさのコンタクトホール(3−2)を開ける〔第1図(
b)〕。Next, a new photoresist is formed and the wiring pads (2-3
) on the first insulating film (3) to open a contact hole (3-2) of a predetermined size [Fig.
b)].
次にプラズマCVD法くより厚さ約300OAのアンド
ープ・アモルファスシリコン(a−8i )m ト約5
001ノリン・ドープ・アモルファスシリコン(n”a
−8i)の連続層からなる半導体層(5)を付着し、ホ
トレジストを用いて素子領域のみに残すようにCDI
(ケミカル・ドライ・エツチング)によりパターンニン
グする〔第1図(C)〕。Next, undoped amorphous silicon (a-8i) with a thickness of about 300 OA was deposited by plasma CVD.
001 Norine doped amorphous silicon (n”a
A semiconductor layer (5) consisting of a continuous layer of -8i) is deposited and CDI is applied using photoresist so as to remain only in the device area.
(Chemical dry etching) [Figure 1 (C)].
次に例えばスパッタリング法やE−Gun蒸着法により
厚さ約1000人のITO(イノジウム・チン・オキサ
イド)等の透明導tiを堆積させ同様なホトレジストを
用いて画素電極(6)を作る〔第11り(d)〕。Next, a transparent conductive layer such as ITO (inodium tin oxide) is deposited to a thickness of about 1000 by sputtering or E-Gun deposition, and a pixel electrode (6) is formed using a similar photoresist. (d)].
このあと真空蒸着法やスパッタリング法により厚さ約5
ooXのMoと厚さ約1μmのアルミニウムを連続的に
付着させ、ホトレジストを用いてソース電極(8−2)
を接続しかつアドレス配線(2−1) ト直交するデー
タ配線(8−1)と、半導体薄膜バターン(5)に重な
りかつ画素電極(6)に接続するドレイン電極(8−3
)を作る。またこのとき、上記した基板周辺のアドレス
配線配線パッド(2−3)部にもこの金属膜からなるパ
ッド電極(8−4)を形成することによって表示装置用
駆動回路基板を完成する1 3″”t”n、aCg″
II(eゝ〕第3図は本発明の他の実施例による表示装
置用駆動回路基板の一画素分を示す断面図である。After this, a thickness of approximately 5 mm is applied using vacuum evaporation method or sputtering method.
ooX Mo and aluminum with a thickness of about 1 μm are continuously deposited, and a source electrode (8-2) is formed using photoresist.
and the address wiring (2-1), which is perpendicular to the data wiring (8-1), and the drain electrode (8-3), which overlaps the semiconductor thin film pattern (5) and connects to the pixel electrode (6).
)make. At this time, a pad electrode (8-4) made of this metal film is also formed in the address wiring wiring pad (2-3) portion around the substrate, thereby completing the display device drive circuit board 13''. "t"n, aCg"
II(e) FIG. 3 is a sectional view showing one pixel of a display device drive circuit board according to another embodiment of the present invention.
□
1 ″。I″ra”ず絶”性“(”)1′・例え
ハ厚さzoooiのMoをスパッタリング法により第1
2゜□。(9)(t*い)L’、2)tJ’@rア7゜
ターノニングしてアドレス配線(2−1)やゲート電極
(2−2)、配線パッド(2−3)を形成しておく。し
かる後前述し九第1の実施例に基づいて第1の導電体層
と第1の絶縁膜の順次付着工程と、この第1の絶縁膜(
3)を前記第2の導電体層(9)のパターンに合せた第
1の絶縁膜パターン(3−1)を形成j シ次い
でgtの導電体層(2)に酸化を施こす工程と、ゲート
電極(2−2)上領域に半導体薄膜パター′1 ノ
(5)を形成する工程および所定の位置に画素電□
極(6)を形成する工程と、データ配線(8−1)とソ
ース電極(8−2)とドレイン電極(8−3)とパッド
電極(8−4)を作る工程を施こすことにより表示装置
用駆動回路基板を完成することができる。□ 1''.I''ra''absolute''property''('')1'.
2゜□. (9) (t*i)L', 2) tJ'@rA7°turning to form address wiring (2-1), gate electrode (2-2), and wiring pad (2-3). put. Thereafter, based on the above-mentioned ninth embodiment, a step of sequentially depositing a first conductive layer and a first insulating film, and a step of sequentially depositing the first insulating film (
3) forming a first insulating film pattern (3-1) matching the pattern of the second conductor layer (9), and then oxidizing the conductor layer (2); A process of forming a semiconductor thin film pattern (5) in the area above the gate electrode (2-2), a process of forming a pixel electrode (6) at a predetermined position, and a process of forming a data wiring (8-1) and a source. By performing the steps of forming the electrode (8-2), drain electrode (8-3), and pad electrode (8-4), the display device drive circuit board can be completed.
尚1本発明の実施例で用いている第1の導電体層は、陽
極酸化可能な金属で、かつ酸化膜とし友ときの光透率に
すぐれている材料であればTagに限らず他の金属を用
いても良い。Note that the first conductive layer used in the embodiments of the present invention is not limited to Tag but may be any other material as long as it is a metal that can be anodized and has excellent light transmittance when formed into an oxide film. Metal may also be used.
またこの酸化手段は陽極酸化法に限らず熱酸化法等を併
用しても良い。Further, this oxidation means is not limited to the anodic oxidation method, and a thermal oxidation method or the like may be used in combination.
更にはアドレス配線の配線パッド上の第1の絶縁膜開孔
は透明導電膜からなる画素電極形成後あるいは半導体薄
膜パターンを加工した後に行っても良い。Furthermore, the opening of the first insulating film on the wiring pad of the address wiring may be performed after forming the pixel electrode made of a transparent conductive film or after processing the semiconductor thin film pattern.
また第1の絶縁膜は5tO2に限らすSiNxやAg2
O3等他の絶縁膜であっても良い。In addition, the first insulating film is limited to 5tO2, SiNx or Ag2.
Other insulating films such as O3 may also be used.
また第3図の実施例では特に大面積基板におけるアドレ
ス配線の抵抗を小さくするのに効果的であシ、このよう
な場合には第2の導電体層はアドレス配線(2−1)と
配線パッド(2−3)には用いるがゲートを極(2−2
)は作らなくても良い。Furthermore, the embodiment shown in FIG. 3 is particularly effective in reducing the resistance of the address wiring on a large-area board, and in such a case, the second conductor layer is connected to the address wiring (2-1) and the wiring. It is used for the pad (2-3), but the gate is used for the pole (2-2).
) does not need to be created.
要するに本発明は酸化可能な金属膜を所望のパターンで
酸化せしめる手段により配線体と絶縁体とに分離するこ
とによりアクティブ・マトリックス型表示装置用駆動回
路基板の配線間相互の短絡を未然に防止するものである
。In short, the present invention prevents short circuits between wirings of a drive circuit board for an active matrix display device by separating an oxidizable metal film into a wiring body and an insulator by oxidizing it in a desired pattern. It is something.
第1囚は本発明による表示装置用駆動回路基板]
の!!遣方法による一実施例を示す工程の平面図、第2
図は本発明の製造方法によって得られた表示装置用駆動
回路基板の一画素分を示す断面図、第1 3図は本発
明の他の実施例を示す断面図・第4図: は一般的
な薄膜トランジスタを用い九表示装置の等価回路図であ
る。
1・・・ig3縁性基飯
i 2・・・第1の導電体層
j 2−1・・・アドレス配線
’2−2 11. ゲ − )4 極
、 2−3−61.@、: 、ド1 3・・
・第1の絶縁膜
3−1・・・第1の絶縁膜パターン
3−2・・・コンタクトホール
4・・・第2の絶縁膜
5・・・半導体薄膜パターン
6・・・画素電極
7・・・オーミック性電極
8−1・・・データ配線
8−2・・・ソース電極
8−3・・・ドレイン電極
8−4・・・パッド電極
9・・・第2の導電体層The first prisoner is a display device drive circuit board according to the present invention]
of! ! FIG. 2 is a plan view of a process showing an example of the
The figure is a cross-sectional view showing one pixel of a display device drive circuit board obtained by the manufacturing method of the present invention. Figures 1 to 3 are cross-sectional views showing other embodiments of the present invention. Figure 4: is a general FIG. 3 is an equivalent circuit diagram of a display device using thin film transistors. 1...ig3 edge base i 2...first conductor layer j 2-1...address wiring '2-2 11. Ge-) 4 poles, 2-3-61. @, : , C1 3...
・First insulating film 3-1...First insulating film pattern 3-2...Contact hole 4...Second insulating film 5...Semiconductor thin film pattern 6...Pixel electrode 7・...Ohmic electrode 8-1...Data wiring 8-2...Source electrode 8-3...Drain electrode 8-4...Pad electrode 9...Second conductor layer
Claims (4)
絶縁膜を順次付着する工程と、 この第1の絶縁膜がアドレス配線及びゲート電極の表面
上を被覆するようにパターン化する工程と、 この第1の絶縁膜パターン下以外の前記第1の導電体層
を酸化して第2の絶縁膜とする工程と、アドレス配線上
の前記第1の絶縁膜の所望の一部に開孔を施こす工程と
、 透明導電膜より構成される画素電極を形成する工程と、 前記ゲート電極上を主領域とする第1の絶縁膜上に半導
体薄膜パターンを形成する工程と、前記アドレス配線と
直交するデータ配線と、このデータ配線の所望箇所より
延設され前記半導体薄膜パターンの一部に接するソース
電極と、一方でこの半導体薄膜パターンに接続をなし他
方で画素電極と接続をなすドレイン電極および前記アド
レス配線上の絶縁膜開孔部上に電極を形成する工程とか
らなることを特徴とする駆動回路基板の製造方法。(1) A step of sequentially depositing a first conductive layer and a first insulating film on one main surface of an insulating substrate, and a step in which the first insulating film covers the surfaces of the address wiring and the gate electrode. oxidizing the first conductor layer other than under the first insulating film pattern to form a second insulating film; and forming a desired pattern of the first insulating film on the address wiring. forming a pixel electrode made of a transparent conductive film; and forming a semiconductor thin film pattern on a first insulating film whose main region is above the gate electrode. a data line perpendicular to the address line; a source electrode extending from a desired location of the data line and in contact with a part of the semiconductor thin film pattern; and a source electrode connected to the semiconductor thin film pattern on the one hand and a pixel electrode on the other hand. 1. A method of manufacturing a drive circuit board, comprising the steps of forming an electrode on a drain electrode for connection and an opening in an insulating film on the address wiring.
いたことを特徴とする特許請求の範囲第1項記載の駆動
回路基板の製造方法。(2) The method for manufacturing a drive circuit board according to claim 1, wherein the means for oxidizing the first conductor layer uses an anodic oxidation method.
徴とする特許請求の範囲第2項記載の駆動回路基板の製
造方法。(3) The method for manufacturing a drive circuit board according to claim 2, wherein Ta is used as the first conductor layer.
ÅのTaを用いたことを特徴とする特許請求の範囲第2
項記載の駆動回路基板の製造方法。(4) The first conductor layer has a thickness of 1000 Å to 3000 Å.
Claim 2, characterized in that Ta of Å is used.
A method for manufacturing a drive circuit board as described in 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60205306A JPS6266665A (en) | 1985-09-19 | 1985-09-19 | Manufacture of driving circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60205306A JPS6266665A (en) | 1985-09-19 | 1985-09-19 | Manufacture of driving circuit substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6266665A true JPS6266665A (en) | 1987-03-26 |
Family
ID=16504769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60205306A Pending JPS6266665A (en) | 1985-09-19 | 1985-09-19 | Manufacture of driving circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6266665A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6462618A (en) * | 1987-09-02 | 1989-03-09 | Matsushita Electric Ind Co Ltd | Production of metallic wiring and production of thin film transistor array |
JPH0385530A (en) * | 1989-08-29 | 1991-04-10 | Sharp Corp | Active matrix display device |
EP0506117A2 (en) * | 1991-03-29 | 1992-09-30 | Casio Computer Company Limited | Thin-film transistor |
-
1985
- 1985-09-19 JP JP60205306A patent/JPS6266665A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6462618A (en) * | 1987-09-02 | 1989-03-09 | Matsushita Electric Ind Co Ltd | Production of metallic wiring and production of thin film transistor array |
JPH0385530A (en) * | 1989-08-29 | 1991-04-10 | Sharp Corp | Active matrix display device |
EP0506117A2 (en) * | 1991-03-29 | 1992-09-30 | Casio Computer Company Limited | Thin-film transistor |
EP0506117A3 (en) * | 1991-03-29 | 1995-09-27 | Casio Computer Co Ltd | Thin-film transistor |
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