JPS6259450A - Signal input circuit - Google Patents

Abstract

PURPOSE:To improve the processing capability of a reception means while minimizing the frequency of a signal input by not inputting signal to the reception means until a comparison means discriminates the transmission of a signal different from an already sent signal. CONSTITUTION:The storage contents of the 1st shift register 4 storing a signal from a serial signal communication circuit 1 and of the 2nd shift resistor 6 storing a signal read by a microcomputer 9 are compared by a comparator circuit 8 in synchronism with a timing pulse outputted from a one-shot circuit 3 by using a signal from a counter circuit 2.Even when a signal is sent to the circuit 8 at any time, until the difference from the signal sent of far is discriminated, no signal is inputted to the microcomputer 9. Thus, the frequency of signal input to the microcomputer 9 is minimized to improve the processing capability of the microcomputer 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the improvement of a signal input circuit of a receiving device, and in particular, it is capable of efficiently inputting encoded signals and increasing the processing capacity of a central processing unit, etc. This invention relates to a signal input circuit.

Conventional technology Conventionally, when controlling various loads by operating switches from a remote point using means such as optical communication or PCM communication, for example,
The following techniques were known. For example, when a switch (not shown) is operated, the operation mode is changed as shown in the time chart of FIG. 6 by the transmitting means 1' shown in FIG.
Each digital encoded signal a, b, or C consisting of a combination of 1" and 0 (hereinafter referred to as "encoded signal")
is converted to

The encoded signal remains unchanged even after the switch (not shown) is operated until the next switch operation is performed. The encoded signal is then directly sent to the receiving means a' together with clock pulses continuously at regular intervals.

For example, according to FIG. 6, when the first switch is operated at time t1, the operation mode is converted to encoded signal a, and t2
The same signal is input to the input section of the receiving means 9' at regular intervals such as at t3, and the same encoded signal a continues until the second switch is operated at 14:00. Thereafter, when the second switch is operated, the encoded signal C is inputted to the receiving means 9', and when the sixth switch is operated, the encoded signal C is inputted to the receiving means 9' at regular intervals.

In this way, some encoded signals are continuously input to the receiving means 9' at regular intervals. Furthermore, the fourth
In the figure, receiving means 9' is constituted by a microcomputer (hereinafter referred to as "microcomputer"), and 11' is an interface 12' which is a load.

Problems to be Solved by the Invention The receiving means 9' performs input processing every time an encoded signal is input, and during this time it is necessary to temporarily stop other processing.

That is, as the input frequency of the encoded signal increases, the processing capacity of the receiving means 9' decreases.

Therefore, when some encoded signal is continuously inputted to the receiving means 9' at regular intervals as in the prior art, the processing capacity of the receiving means 9' naturally decreases.

Means for Solving the Problems The present invention solves the above-mentioned problems, and includes a first storage means for storing the first signal from the transmitter so as to be input only when a new signal is input. , a second storage means for storing the second signal read into the reception means, and the storage contents of the first storage means and the second storage means are compared to determine a difference, and the first signal is read into the reception means. The control comparison means constitutes a signal input circuit.

Operation With the above configuration, the first storage means stores the first signal when it is input from the transmission means, and the second storage means stores the second signal read into the reception means. The first and second storage means output the first signal and the second signal to the comparison means, respectively.

The comparing means compares the first signal and the second signal, and if they are different, reads the first signal into the receiving means.

Therefore, a signal is input to the receiving means only when a new signal is transmitted.

Example FIG. 1 is a circuit diagram showing a preferred embodiment of the present invention.

1 is a serial signal communication circuit as a transmitting means;
This is a circuit that communicates an encoded serial signal consisting of predetermined bits depending on switch operation or volume operation status using electrical signals or optical signals. For example, a device installed in a car that remotely controls audio equipment, air conditioner equipment, door lock equipment, power window equipment, etc. in response to the operation of a central switch located in the center of the steering wheel or a central switch located in the armrest. There are multiplex communication circuits used for

2 is a counter circuit, and 6 is a one-shot circuit, which constitute timing means. To explain in detail, the counter circuit 2 is as follows.
This circuit is connected to the serial signal communication circuit 1 and counts clock signals synchronized with the serial signal, and counts the number of bits of the serial signal. For example, if the serial signal is an 8-bit signal, the clock signal is counted 8 and the signal is output to the one-shot circuit 5 at the subsequent stage. Further, the one-shot circuit 6 outputs a timing pulse in response to the signal input from the counter circuit 2.

Note that the one-shot circuit 3 can be omitted as appropriate and the output signal of the counter circuit 2 can be used as a timing pulse, and the decision as to whether or not to omit it can be made, for example, by designing the width of the timing pulse. It may be determined according to the specifications.

4 is a first shift register, 5 is a first gate circuit,
The first shift register 4 and the first gate circuit 5 (!: constitute a first storage means. To be more specific, the first shift register 4 is a circuit for converting a serial signal into a parallel signal. 1. The first serial signal input section S, I, 1 and the first clock signal input section CL of the shift register 4.
OCK1 is connected to serial signal communication circuit 1, respectively. Further, the first gate circuit 5 includes AND circuits 51 to 58.
One input section of each is connected to the parallel signal output section of the first shift register 4, and the other input section is connected to the output section of the one-shot circuit B.

6 is a second shift lens star, 7 is a second gate circuit,
The second shift register 6 and the second gate circuit 7 constitute a second storage means. The second shift register 6 and the second gate circuit 7 have the same electronic element configuration as the first shift register 4 and the first gate circuit 5, respectively, and the difference is that the second serial signal input of the second shift register B Sections S, I, 2 and second clock signal input section CLOC
This is the point where each K2 is connected to a microcomputer 9, which will be described later.

8 is a comparison circuit as comparison means, which includes exclusive OR circuits 81 to 88, an OR circuit 89 and an AND circuit 80.
Consists of.

One input section of the exclusive OR circuits 81 to 88 is
It is connected to each output section of the first gate circuit 5, and the other input section is connected to each output section of the second gate circuit 7. or,
Each output section of the exclusive OR circuits 81 to 88 is connected to an OR circuit 89, and the output section of the OR circuit 89 is connected to an AND circuit 80.
The other input part of the AND circuit 80 is connected to the timing pulse output part of the one-shot circuit 5. Further, the output section of the AND circuit 80 is connected to the update signal input section IRQ of the microcomputer 9.

9 is a microcomputer as a receiving means. The microcomputer 9
In addition to the second shift register 6 and comparison circuit 8, a fifth shift register 10, which will be described later, is connected to a load 12 via an ink face 11.

10 is a third shift register, and the first gate circuit 5
Converts the parallel signal output from the to a serial signal,
This is a circuit for inputting to the microcomputer 9, and is interposed between the first gate circuit 5 and the microcomputer 9.

Next, the operation of the preferred embodiment of the present invention having the above configuration will be described in detail with reference to the time chart shown in FIG.

For example, assume that the first switch is operated at time t.

Then the operation mode changes to the time chart shown in Figure 2) (100)
is converted into the encoded signal a shown in FIG.
and the first serial signal input section S of the first shift register 4 at regular intervals.

1 is input. At this time, simultaneously with the encoded signal, the clock pulse signal shown in the time chart (101) in FIG.
It is input to CK 1 and counter circuit 2. The counter circuit 2 outputs a clock pulse signal to the subsequent one-shot circuit 3 every predetermined count.

The one-shot circuit 3 outputs timing pulses shown in the time chart (102) in FIG. 2 at time t7 and time t11 according to the signal from the counter circuit 2 or 6.

The comparing means 8 compares the contents of the first shift register 4 and the second shift register 6 in synchronization with the timing pulse. For example, at time t7, the stored content of the first shift register 4 is a coded signal a, but the stored content of the second shift register B is a coded signal C, and since the two are different, the comparing means 8 is shown in FIG. The update signal shown in the time chart (103) is output to the microcomputer 9.

The microcomputer 9 executes a subroutine for interrupt input processing when the update signal is input.

Then, for the third shift register 1D at time t8, the second
The read signal shown in the time chart (104) in the figure,
A clock pulse signal shown in the time chart (105) in FIG. 2 is input, and a serially converted encoded signal a shown in the time chart (106) in FIG. 2 is read into the microcomputer.

When the reading process is finished, the microcomputer 9 starts the second reading process at time t.
For the shift register 6, the time chart (1
The clock pulse signal shown in 05) and the encoded signal a shown in the time chart (107) in FIG. 2 are input, and the stored contents of the second shift register 6 are updated. When the microcomputer 9 finishes executing the subroutine for the series of input processing, it performs each control based on the read encoded signal.

As described above, in the preferred embodiment of the present invention, the microcomputer 9 executes signal reading processing only when a new encoded signal is transmitted from the serial signal communication circuit 1, so that the processing capability of the microcomputer 9 is improved. That will happen.

Effects of the Present Invention As described above, the present invention includes a first storage means for storing the first signal from the transmitting device, a second storage means for storing the second signal read into the receiving means, and each of the above-mentioned memories. The present invention is characterized in that the signal input circuit is constituted by a comparing means which reads the first signal into the receiving means when the contents are compared and a difference is determined.

Therefore, even if a signal such as a coded signal is transmitted from time to time, the signal is not input to the receiving means until the comparison means determines that a signal different from the signals transmitted up to that point has been transmitted. Therefore, the frequency of signal input to the receiving means can be kept to a minimum, and there are excellent effects in that the number of interrupt inputs to the receiving means can be reduced and the processing capacity of the receiving means can be improved by blocking interrupt inputs.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram showing a preferred embodiment of the present invention. FIG. 2 is a time chart of the preferred embodiment of the present invention shown in FIG. FIG. 3 is a time chart according to the prior art. FIG. 4 is an electrical circuit diagram showing a conventional technique. 1...Serial signal communication circuit, 2...Count circuit, 3...One-shot circuit, 4...°・
・First shift register, 5...First gate circuit, 6
...W2 shift register, 7...2 gate circuit, 8...comparison circuit, 9...microcomputer, 10...3rd shift register. that's all

Claims (1)

[Claims] Comparing the first storage means for storing the first signal from the transmitting device, the second storage means for storing the second signal read into the receiving means, and the storage contents of the first storage means and the second storage means. and comparing means for determining the difference between the signals and controlling the reading of the first signal into the receiving means.