JPS6258718A - Pulse output circuit - Google Patents

Abstract

PURPOSE:To improve the rising characteristic of an output pulse by amplifying reversely a high-pass component at the rear edge part of an input pulse and adding a circuit to supply it to the base of a terminal transistor to correspond to a high speed pulse. CONSTITUTION:For the differentiation of an input signal, a capacitor C3 and a resistor R4, and a transistor (TR) Q4 and a diode D3 are added to a device. An input signal 1 is inverted at a TR Q1, driving TRs Q2 and Q3. Also, the high-pass component at thr trailing edge of the input signal is introduced to the TR Q4 through the capacitor C3 and raises steeply the base potential of the TR Q2, supplying a sufficient driving current on it. Therefore, the output pulse, in which a time delay is not generated, can be raised steeply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-speed pulse output circuit for an apparatus including a Direckle pulse generation section.

[Background of the invention]

As a pulse output circuit that has a simple circuit and can produce sufficient output amplitude, a combinational single-ended pushpull circuit (complementary SEPP circuit) has been proposed. The circuit drives the final stage amplification transistor circuit.

For this reason, the rise of the output pulse slightly lags the fall of the input pulse, making it unsuitable for outputting high-speed pulses. Furthermore, in conventional circuits, when emphasis is placed on high-speed pulses, problems arise such as an increase in current consumption, a significant increase in circuit scale, and a decrease in output amplitude.

FIG. 2 is a circuit diagram showing a pulse output circuit of a conventional complementary SEPP circuit. In the figure, a pulse signal introduced from an input terminal (1) is supplied to the base of a common emitter type transistor (Q, ) through a parallel circuit of a resistor (R1) and a capacitor (C1). This signal is inverted by the transistor (Q,), and the signal taken out from its collector is the final stage transistor (Q,).
Q2) , (Q,) are driven.

At this time, in the off direction of the transistor (q,) (falling edge of the input signal), the driving capacity of the next stage transistor is 1.
Therefore, the rise of the pass A signal obtained at the output terminal (2) is delayed from the fall of the input signal by the time (tlt!) shown in Figure 3.As a countermeasure, generally the final stage transistor Pair (Q, l.

Although it is possible to shift (Q,) to a Darlington connection, for example, if two stages are connected and the output amplitude is 2・■BE
(However, there is a drawback that V8ε (voltage between the base and emitter of the t transistor) will drop considerably. Note that (R2
), (R11) is a resistor, (rl,), (C2)
is a diode, (C2) is a diode, (+Bl is a power supply voltage).

[Purpose of the invention]

It is an object of the present invention to solve the above-mentioned problems and provide a high-speed pulse output circuit for /J with excellent rise and fall response characteristics.

[Summary of the invention]

In order to cope with high-speed pulses, the present invention adds a circuit that inverts and amplifies the high frequency component (('A'li component waveform)) at the trailing edge of the input pulse and supplies it to the base of the final stage transistor. As a result, the base current of the I.Landisque is increased to improve the rise characteristics of the output pulse.

〔Example〕

FIG. 1 is a circuit diagram showing a pulse output circuit according to an embodiment of the present invention. The elements added in FIG. 1 to FIG. R4), transistor (Q4) and diode (
C3).

Now, the pulse signal supplied from the input terminal (1) is inverted by the transistor (Q,), which drives the final stage transistors (Q,) and (Q3) as described above. Further, the high-frequency component at the falling edge of the input pulse signal is introduced into the transistor (Q4) via the differential capacitor (C3), and thereby the transistor (q2)
The base potential of the transistor (
Supply sufficient driving current to Q2). Therefore, the output pulse can rise quickly without any time delay.

In addition, in the above embodiment, the final stage I transistor is npn and pn.
Although this invention relates to a combination with an np, the present invention can be similarly applied to a combination of a pnp and an npn. Supplies the base of the stage transistor.

〔Effect of the invention〕

As described below, according to the present invention, the trailing edge of the input pulse is differentiated, inverted and amplified, and then supplied to the final stage transistor as the base current, so that the base is sufficiently driven.
Not only can a circuit with layered output pulse rise characteristics be realized, but a sufficient output amplitude can be ensured, and current consumption increases only slightly. Furthermore, according to the present invention, the above characteristics can be achieved with a slight increase in the number of parts.
Implementation has great effects.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a pulse output circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional circuit, and FIG. 3 is a waveform diagram of its human power and output pulses. In the figure, (1) is the input terminal, (2) is the output terminal, (Ql)
~(Q4) Ha!・A transistor, (C0) to (C2) are capacitors, (R3) to (R4) are resistors, (Dll,
(C2) is a diode. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Patent Attorney Tadashi Sato Figure 2 Figure a

Claims (1)

[Claims] What is claimed is: 1. A pulse output circuit equipped with a complementary SEPP circuit, characterized in that a circuit is added that differentiates the trailing edge of an input pulse, inverts and amplifies it, and then supplies it as a base current of a final stage transistor.