JPS6258672A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To stabilize the storage charge holding characteristics, by providing a writing transistor of a gain cell within a substrate. CONSTITUTION:A substrate 100 is provided therein with a writing transistor 104 controlled by a write-word line 109. The source of the transistor is connected to a read/write but line 107 and a charge-storage capacity 110 is provided in the drain. A sensing transistor 103 controlled by charges stored in the charge- storage capacity 110 and a reading transistor 102 controlled by a read word line 109 are provided between the bit line 107 and a reference potential 101. By providing the change-holding transistor 104 within the substrate in this way, the storage charge holding characteristics can be stabilized. Further, since the operation of the transistor is controlled by stored charges themselves instead of capacitive coupling, the operation of the memory can be prevented from being effected by any variation in capacity values due to variation in manufacturing processes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory cell constructed of dynamic memory cells (hereinafter referred to as gain cells) having an internal amplification function.

[Conventional technology]

Figure 4 (a) and (b)
EE Tran-qactions ON File
ectron Device day, Vow, E
T)-32°No, 2. February 1985
Magazine (PP, 258-281)! This is a top view and cross-sectional view showing conventional gay/cell gold, π4 Figure (b) M %
4(a) is a sectional view taken along the IVB-IVB plane in FIG. 4(a). FIG. 5 is an equivalent circuit diagram of the gain cell shown in FIG. 4. ! In Figure 4, (!
(2) is the diffusion wiring that forms all the bit lines for continuous output (READ BIT L engineering NK), (3) is the diffusion wiring that forms the bit line for writing (WR engineering TE).
BIT L Engineering NK) f Aluminum wiring to be formed, (
4) Read (word line for 7 (READ “VO-RD
3rd layer polycrystalline silicon wiring forming (L engineering NE), (5
) is the second layer polycrystalline silicon wiring that forms the write input word line (W'F TFWORT L), (6) is the isolation oxide/arsenic film, (7) is the first @ polycrystalline Polysilicon transistors (SOX) formed on silicon wiring
POLYSIL:rcONTRANf'+l5TOR)
, its source +81 HW'RITEBITL +31 j is connected, and its drain (911) is connected to the charge storage section (CHARGFi 5TORAGE) 101
(7) It is an il pole. 01) is formed in the substrate h
Read transistor (BULK 5EN-8ETRA
NSTSTOR), and its drain is connected to the VDD wiring (
1), the source is READ B, TL, and NE (connected to 21).

Next, in Figure 5, C1 is RKAD WORD
L engineering NE (41 and so engineering POLYS engineering OON TR
Consisting of the drain (9) of ANS engineering 5TOR (7), Saharu CHARGE 5TORA (TE flol electric capacity, C21d C!HARGK 5TOFtA
GE section + 10) stray capacitance, VTP HS○
OLYS CON TRANS 5TOR (threshold voltage of 71, VTB n BULK sgNs
g is the threshold voltage of TRANsrsToR (11), VRW n RRJD WORD IJNE +
41 high potential level.

Next, the operation will be explained. During write operation, WFI TF', WORD NE tel and READ WO
IRD L engineering NE +41 and both are set to high potential, and WR
Apply the information potential you want to write to Engineering TE B Engineering T Edit NE +31. When the capture is completed, first WR Engineering TK WO
RD L engineering NE +51 to low potential, shake and READ
WORD LENG NK +41 From this point on, it is written to C) TA-RGE 5TORAGE 001 and the potential (vH) is held at f'1. At this time, B
The following equation is given as a condition for ULK 5KNSE TRANs 5TOR (11) not to conduct.

Va −01VRw/ (C, +O:)<VTn
... [1) Ma1ko, CHARGE 5TO
RA()E flol 1 □It level ((V)
If 1 is written (in the holding state, it becomes -CI VRw/(C1+C2), so polysilicon, transistor (So engineering POLYS engineering engineering C!ON TRANS engineering 5ToR) ( The following equation is given as a condition for 7) not to conduct.

-C! I VRw/ (C1'+02) < -VT
P... [2] Therefore, ++ On
It does not become lower than the potential lamp -VTP in the level holding state.

From here, during read operation, that is, W[TE WORD
L engineering NE +51 is low level, READ WORD L
When NE +41 is high level (VRW), FIULK SE of the memory cell that was written "Ol level f" I?
JS11fl TRANS 5TORα℃ is not conductive under the following formula.

-VTP + CIVRw/(Oz+02) <VTR
- (31 [1') equation K] The following relational expression is derived by combining the [3] equation.

VH-VTB<01VRw/(C1+04)<VTP
+VTR=-(41 As explained above, 1) From this point, it is important to control the capacitance value and potential so as to satisfy Equation 41.
A memory operation is performed f7.

[Problem that the invention seeks to solve]

It is designed to be more sophisticated than a conventional gain cell, so
1) Accurately perform cHARGE 5TORA every time to perform all memory operations, so as to satisfy all the relationships in equation [4]
It is necessary to control the capacitance value of the -/G[il] polysilicon transistor's 11-current current is less controllable than that of a transistor created in the bulk. There are problems such as 1 characteristic, anxiety, and 2 remaining problems.

This invention was made in order to solve all of the above-mentioned problems, and it is possible to perform memory operation without being affected by the capacitance value of the CHARGE 5TORAGE section, and to ensure stable memory load retention. The object of the present invention is to obtain a semiconductor memory device composed of gain cells.

[One-shot means to solve the problem] This invention S related semiconductor memory device, WR Engineering TE WO
RDL engineer? A write transistor controlled by the JP is formed in the substrate, the source of the write transistor is connected to the bit line (used for both writing and continuous output), and the drain is held as storage information or charge, A polysilicon transistor controlled by its storage charge and R
A polysilicon transistor controlled by the EAD WORD L element 1 is connected in series between the bit line and the 6Sg potential, and is constituted by a gain cell.

〔substitute〕

The semiconductor memory device according to the present invention does not rely on capacitive coupling.
Since the transistor operation is controlled by the storage charge (potential) itself, the memory operation is not affected by capacitance value fluctuations caused by manufacturing process fluctuations.
Since the holding transistor is formed within the substrate,
Storage charge retention characteristics are stabilized.

[Embodiment 2 of the Invention] An example of a paddle according to the invention will be described below with reference to the drawings. 1st
In the figure, (101) is the reference 1! made up of the second polysilicon layer! It is the source line (102).

(103) /'ip channel polysilicon transistor, (XO4) ke p-substrate (SUB 5TRA
TE) Buried contact formed at (loo)°, (10
6) H bit line formed from H aluminum wiring (lo'7
) and the second polysilicon layer, (10
8) P-channel polysilicon transistor (10
2) and (103), (109) is the first
Word line (WL), (1
10) constitutes a reference power supply line (101) and the gate of a p-channel polysilicon transistor (103). This is a charge storage capacitor formed between the first diffusion layer and the (111) silicon layer.

In addition, FIG. 1(a) is a d plan view, and FIG. 1(b) is a 1st
It is a cross-sectional view taken along the line ■B-iB of the figure (al).

FIG. 2 shows the equivalent circuit factor of the embodiment shown in FIG.

From FIG. 2, it can be seen that this is a modification of a three-transistor type dynamic memory cell.

The operation will be explained based on the timing diagram shown in FIG. To write the ゛°1°° level, set the word line (1o9) to a high potential and apply the HI11 level to the bit line (lO7). At that time, the write transistor (104) associated with the selected word line (109) becomes conductive.
The potential of the bit line (107) is transmitted to the charge storage capacitor (110). When the word line (109) returns to OV, the transistor (104) becomes non-conductive and the II II level is held in the charge storage capacitor (110). When the word line (109) is set to a negative potential, readout EdJ f 'lE
is executed. When the charge storage capacitor (xxo) is written high, the sensing polysilicon transistor (103) becomes non-conductive, and the readout polysilicon transistor (103) becomes non-conductive and is controlled by the word line (109). silicon·
Even if the transistor (102) becomes conductive, the resistance between the base power supply line (101) and the bit line (10'7) remains high, and the potential of the bit line (10'7) does not change. On the other hand, if the charge storage capacitance (110) is taken into account, then the polysilicon transistor (10
3) becomes conductive, so when the word line (109) becomes negative potential, the reference power line (1o1) and the bit line (10'
/) becomes a low resistance state, and the bit line (10'i'
) is charged in the direction of the potential of the reference power line (101) and discharged (discharged to the ground potential in the description).

Since the storage potential of the charge storage capacitor (uni-O) and the amplification direction of the potential of the bit line (10'7) at the time of successive readout match, the 2I is read to the unselected bit line (1o7) at the time of writing.
-1'r-Charge The charge of the 8' term capacitance (1 unit) is fully amplified and the charge storage is borrowed (110). 'h bit line (1
By forcibly applying voltage from the outside only to the selected bit line (10'/) and word line (10'/), the selected bit line (10'/) and word line (10'
9) It becomes possible to rewrite only the information in the memory cells at the intersections.

In the above embodiment, the fl
7: Although shown is a structure composed of n-channel transistors, it may be formed by forming a p-channel transistor on an n-type substrate, or may be formed using a CMOS process.

Furthermore, although the direction of the charge f17: stored in the charge storage capacitor and the amplification of the pit line potential at the time of reading do not necessarily match, the same effect as in the above P embodiment can be achieved by appropriately changing the peripheral circuit.

〔Effect of the invention〕

As described above, according to the present invention, since the write transistor of the gain cell is a transistor on the substrate, the storage charge retention characteristic is stable, and the read transistor and the sense transistor controlled by the storage charge are used. Since it is installed in series between the reference power supply line and the bit line, precise control of the capacitance of the node in the memory cell is no longer necessary.
This has an effect that a highly reliable semiconductor memory device cannot obtain.

[Brief explanation of drawings]

Fig. 1(a) il''j A plan view of a semiconductor 1 storage device according to an embodiment of the present invention, Fig. 1(1)) h Fig. 1(a)
Figure 2 is an equivalent circuit diagram of this embodiment, Figure g113 is an operation timing diagram of this embodiment,
FIGS. 4(a) and 4(b) are a plan view and a sectional view of a conventional semiconductor memory device, and FIG. 5 is an equivalent circuit diagram of this conventional device. In the figure, (100) is a semiconductor substrate, (101) is a reference power supply line, (102) is a transistor for continuous lighting, (10 is
3) g-1 sense transistor, (104) [Write transistor, (xo7) or pit line, (108
) is a node, (109) H word line, (110) tri
It is charge storage capacity. In addition, the -+8- digits in the figure indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A first layer polysilicon layer formed on a semiconductor substrate via an insulating film and forming a word line; a write layer formed in the semiconductor substrate using the word line formed of the first layer polysilicon layer as a gate; a read transistor formed in a second layer polysilicon layer formed so as to use the word line as a gate and connect to the source of the write transistor, and use the connecting portion as a source; The drain of the reading transistor is connected to the gate, the drain is connected to a reference power line made of a part of the second polysilicon layer in the second polysilicon layer, and the source is connected to the drain of the read transistor at a node. a sense transistor formed so as to be connected to the second layer polysilicon layer, a charge storage capacitor formed between the drain of the write transistor and the reference power supply line and the drain of the sense transistor; A plurality of the above-mentioned words each having a plurality of memory cells arranged in the X and Y directions each having a bit line made of a metal layer connected at the source of the read transistor and provided through an insulating film in other parts. A semiconductor memory device formed at a three-dimensional intersection of a line and a plurality of bit lines.