JPS6258356A - Dma controller - Google Patents

Abstract

PURPOSE:To give a designation/start instruction to a DMA subject address space just in a single time by storing the transfer direction information of a single bit related to the DMA transfer in each address of a high-speed access memory and reading these transfer direction information synchronously with advance of addresses to supply them to devices. CONSTITUTION:A read/write control circuit 7 incorporates a high-speed memory having a satisfactorily high-speed access time compared with memories 4 and 5 and can receive an access from a controller DMAC1 via an address bus. At the same time, the circuit 7 undergoes the chip selection via a signal during DMA transfer. The information of a singe bit corresponding to the transfer direction of each address is stored in each address of the high-speed memory. When these addresses receive addresses successively, 1 or 0 is delivered from the high-speed memory for each address. Then read-out signals are supplied to a memory 4 as R signals and to a memory 5 as W signals respectively. In a DMA transfer mode the entire transfer area is totally designated to the DMAC1. Thus the transfer areas are designated just in a single process.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a DMA control device that is capable of specifying a transfer direction for each address constituting a DMA target address space.

(Summary of the Invention) The present invention stores 1-bit transfer direction information related to DMA transfer of the address in each address of a high-speed access memory, reads this in synchronization with address increment, and transmits it to mutual equipment related to DMA transfer. By supplying this information, even if the transfer direction differs for each address, the designation of the DMA target address space and the activation command can be performed all at once.

(Prior art and its problems) FIG. 11 shows the hardware configuration of a conventional DMA control device.

In the figure, a direct memory access controller (hereinafter simply referred to as DMAC) 1 is represented by, for example, Motorola's 68/44, etc.
Upon receiving a designation of a DMA target address space and a DMA transfer activation command from the PU, a series of address signals constituting the address space are sequentially sent onto the address bus.

Chip selection circuits 2 and 3 each have DMACI to DM
In response to the arrival of the A medium signal, a chip select signal is formed by decoding a predetermined upper digit of the address bus, and is supplied to the corresponding memories 4 and 5, respectively.

In addition, an R/W signal is output from the DMAC 1 for each addressing, and by inverting this signal with an inverter 6, an R signal is sent to one of the mutual memories 4 and 5 that performs DMA transfer, and to the other. W signals are respectively supplied.

Now, as shown in FIG. 12, memory A4 and memory B5 are allocated to the same address space, and for address spaces $0000 to $1FFF, from memory A to memory B, and from address space $2000
~For $3FFF, DM from memory B to memory A.
Assume that A transfer is performed. In this case, the program for DMA transfer in the CPU is expressed as shown in the flowchart of FIG. - That is, first, set the transfer area for DMAC1 to $00.
00 to $1 FFF, and at the same time set the R/W signal to read (step 1300).

Next, the DMAC 1 is instructed to start DMA transfer (step 1301).

Next, when the DMA transfer from memory 8 to memory B is completed, the transfer area for DMAC1 is set to $20.
00 to $3FFF, and at the same time set the R/W signal to write (step 1302>).

Next, a DMA transfer activation command is given to DMAC1 (step 1303).

In this way, in the conventional DMA control device of this type,
Even when performing DMA transfer to a continuous series of address spaces, if the transfer direction is partially different, the transfer area must be reset for each area with the same transfer direction. Therefore, when the transfer direction is different for each small area within a series of address spaces, the transfer area setting process is performed frequently, resulting in the problem that the benefits of high-speed transfer by DMA transfer cannot be fully utilized. There was a point.

(Object of the Invention) The object of the present invention is that even if a series of address spaces is further divided into small spaces with different transfer directions, the transfer area setting process Z111r for the DMAC can be sufficient. The object of the present invention is to provide a DMA control device that can fully utilize the advantages of speeding up DMA transfer.

(Structure and Effects of the Invention) In order to achieve the above object, the present invention sequentially generates a series of corresponding address signals based on DMA target address space information given from the CPU, and uses these signals for mutual communication related to DMA transfer. address management means for supplying the device to the device; having a high-speed memory that can be accessed by the address signal, and each address of the memory has a D address of the address;
One bit of transfer direction information related to MA transfer is stored, and the transfer direction information read out corresponding to each address signal is stored in D.
It is characterized by comprising: a transfer direction management means for supplying mutual devices related to MA;

According to such a configuration, even if a series of address spaces is further divided into small spaces with different transfer directions, the transfer area setting process can be completed only once, and DMA transfer It is possible to fully utilize the advantages of speeding up.

(Description of Embodiments) FIG. 1 shows the hardware configuration of a DMA control device according to the present invention. In addition, in the figure, the same reference numerals are given to the same components as those of the conventional example, and the explanation thereof will be omitted.

The feature of this embodiment is that the read/write control circuit 7 generates the R/W signal.

As shown in FIG. 2, the read/write control circuit 7 controls the memory Δ4. A built-in high-speed memory 71 having a sufficiently faster access time than that of memory A4.B5 is built-in. It is allocated to the same address space as memory B5.

In addition, the seven high-speed memories are connected to DMA via the address bus.
It is made accessible by C1 and is chip selected by the DMA signal.

As shown in FIG. 3, each address of the seven high-speed memories stores 1-bit information corresponding to the transfer direction of each address. Therefore, by sequentially accessing each address, the high-speed memory 71 l(111 or O'' is output for each address.Then, the read signal is sent to the memory A4 as an R signal, and inverted by the inverter 72 and supplied to the memory B5 as a W signal. Ru.

Note that the high-speed memory 71 may have various configurations, such as a ROM into which transfer information has been loaded in advance, or a RAM in which transfer direction information is written during initial processing of the system.

FIG. 4 is a flowchart showing the contents of DMA control processing performed by the CPU. As shown in the figure, in this embodiment, even if a series of address spaces is divided into small spaces with different transfer directions, the transfer area is first divided into a series of address spaces $oooo to $3FFF. (step 400), and then it is only necessary to give a transfer activation command to DMAC1 only once (step 401).

As described above, in this embodiment, if transfer direction information is stored in each address of the high-speed memory in advance,
At the time of DMA transfer, it is sufficient to specify the entire transfer area to DMAC1 at once. Therefore, even if a series of address spaces is divided into many transfer areas and each transfer area is different, The transfer area setting process only needs to be performed once, and the advantages of speeding up the DMA transfer can be fully utilized.

In the above embodiment, the entire address space is divided into two small areas and DMA transfer is performed.
Even if the entire address space is further divided into a large number of small areas as shown in the figure, it is of course only necessary to store transfer direction information for each small area in a high-speed memory as shown in Fig. 6. .

Furthermore, in the above embodiment, the case was explained in which DMA transfer was performed between two memories, but as shown in FIG. 7, n memories M, .
When connecting Mn and sequentially transferring data read from each memory to another memory, R/W control circuits RW + to R connected to each memory as shown in FIG.
The data transfer direction information for each address area is stored in the high-speed memory in Wn as shown in FIG. 10, and the non-inverted output of the high-speed memory is stored in each memory M1 to M as shown in FIG.
It is sufficient to supply it to the R/W terminal of n.

In this case as well, the DMA transfer only needs to be started once, so no time is wasted on CPU processing.

As described above, according to the present invention, the transfer area setting process and activation command for the DMAC can be completed only once, and the overall transfer time can be shortened compared to the case of transfer using the conventional DMAC. It is possible to fully utilize the benefits of transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the hardware configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing details of the read/write control circuit, FIG. 3 is a memory map showing the storage contents of the high-speed memory, and FIG. 4 is a block diagram showing the details of the read/write control circuit. is a flowchart of DMA control processing performed by the CPU, FIGS. 5 and 6 are memory maps explaining an example when the DMA transfer area is divided into many small areas, and FIG. 7 is a flowchart of DMA transfer between multiple memories. FIG. 8 is a memory map of a high-speed memory when DMA transfer is performed between the same number of memories, and FIG. 9 is a diagram showing details of each read/write control circuit RW. , 10th
The figure shows each high-speed memory M. This is a memory map showing the memory contents of ~Mn. 1...DMAC 2, 3...Chip selection circuit 4.5...Memory 7...Read/write control circuit 71...
・・・・・・High-speed memory Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 8 Figure 9/Figure 1O Figure 72 Procedural amendment June 12, 1985

Claims (1)

[Claims] (1) Address management means that sequentially generates a series of corresponding address signals based on DMA target address space information given from the CPU and supplies them to mutual devices involved in DMA transfer; accessible by the address signals; It has a high-speed memory, and each address of the memory has a D of the address.
One bit of transfer direction information related to MA transfer is stored, and the transfer direction information read out corresponding to each address signal is stored in D.
A DMA control device comprising: transfer direction management means for supplying signals to mutual devices related to MA;