JPS6257046A - Memory protection system - Google Patents

Abstract

PURPOSE:To attain effective memory protection even in a device obtaining an absolute address as the result of address conversion by providing an address area storage means, an address information storage means, a comparison means and a switching means, etc. CONSTITUTION:The upper limit address and lower limit address of a main storage device are stored in a memory protection buffer MGB as an address area storage means and they are read by comparators COM1, COM2. In such a case, a high-order bit of an address ADR equivalent to an absolute address stored in an address register ADRR is fed to the comparators COM 1, 2, where a value decided by the high-order bit is compared with the upper limit address and the lower limit address, and when the result shows outside of the area, a NOR gate NOR outputs logical '0'. Then a switch ZNX is controlled and the output of a zone register is changed into the designation of no write byte forcibly and the destruction of other operating system area due to software malfunction is prevented to protect the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory protection method, and more particularly, the present invention relates to a memory protection method, and more particularly, the present invention relates to a memory protection method, and more particularly, the present invention relates to a memory protection method that protects memory between a peripheral device and a main memory device by each input/output instruction from a program controlled by each of a plurality of operating systems. The present invention relates to a memory protection method in a virtual input/output processing device that controls data transfer and obtains an absolute address as an address translation result.

[Conventional technology]

In a virtual input/output processing unit (hereinafter simply referred to as an input/output processing unit) that executes multiple operating systems, there is a large speed gap between the peripheral VT device and the input/output processing unit, so multiple operating systems perform input/output processing. In these cases, each operating system and each program running under its control divides the amount of space it uses in main memory from that of the other operating systems. It is necessary to ensure that they do not corrode each other.

On the other hand, address translation methods for virtual machines include methods in which a virtual address is converted into a real address (relative address within the operating system) and then an absolute address is obtained by adding a base address specific to the operating system to this address. , a method is known that speeds up address translation by converting virtual addresses to absolute addresses all at once.

In a virtual input/output processing device that employs the former address conversion method, the memory area can be easily checked by comparing its memory size and real address in accordance with the operating system.

[Problem that the invention seeks to solve]

However, with virtual input/output processing units that adopt the latter address translation method, such memory protection methods cannot be used and there is no other effective means, so software malfunctions may cause other operating systems to There is a problem in that it destroys the system area.

SUMMARY OF THE INVENTION An object of the present invention is to provide an effective memory protection method for a virtual input/output processing device in which an absolute address is obtained as a result of address translation.

[Means for solving problems]

The memory protection method of the present invention controls data transfer between peripheral devices and main memory based on input/output commands from multiple operating systems, and performs virtual input/output processing in which an absolute address is obtained as an address conversion result. In the memory protection system in the device, an address area storage means for storing in advance an upper limit address value and a lower limit address value defining an area on the main storage device used by each of the operating systems corresponding to the operating system; , an address information holding means for holding address information associated with an access request from the virtual input/output processing device to the main storage device, and a write byte position designation to the main storage device corresponding to the access request. zone holding means; identifier holding means holding a program identifier of an operating system to which the input/output instruction that generated the access request belongs; reading means for reading out the address area storage means using the program identifier; address comparing means for comparing the address upper limit value and address lower limit value and the address information, and determining whether or not the address information is within the windowed area based on the comparison result by the address comparing means. and switching means for permitting the access request when the access request is within the area, and forcibly changing the output of the zone holding means to specify no write bytes when the access request is outside the area.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing a hardware environment to which this embodiment is applied.

First, referring to FIG. 2, an input/output processing unit OP and an arithmetic processing unit EPU are connected to a main storage unit iMMU via a system control unit SCU.

The input/output processing device 10P controls data transfer between a peripheral device (not shown) and the main storage device MMU based on input/output instructions taken from the main storage device MMU. Such input/output instructions are output from each program controlled by each of the plurality of operating systems on the main storage device MMU. Peripheral device is input/output processing unit IOP
Since the operating speed is slow compared to the operating system, in order to improve the total processing speed, multiple operating systems are executed in parallel. Therefore, the input/output processing device 10P is a virtual machine, and address conversion from virtual addresses to absolute addresses is performed by the arithmetic processing unit EPU.

FIG. 3 shows the input/output processing device ■ shown in FIG.

1 is a detailed block diagram of P, including a memory access control unit MAC and a control memory unit CM.
It consists of a channel unit (CDU) and a channel unit (CHU).

Is the channel unit CHU an input/output processing bag? &10P, and performs a data buffering operation between the peripheral device and the control memory unit CMU and channel data unit CDU connected via bus BUS.

The control memory unit CMU is a unit that stores firmware for controlling data transfer, takes out input/output instructions from the main memory MMU, decodes them, and based on the decoded results, creates a channel unit CHU, a channel data unit CDU, and a memory. Performs various controls of the access control unit MAC.

The channel data unit CDU buffers the transferred data in correspondence with the channel unit CHU under the control of the control memory unit CMU.

Next, referring to FIG. 1 showing one embodiment of the present invention, the memory protection method of this practical example is based on the memory protection buffer MOB
, two comparators COMI and C0M2. Identifier register 5IDR, address register ADRR, request code register RQCR, zone register ZONR, data register DTAR, NOR gate NOR, control circuit C0
NT and seven switches MXI to MX6 and ZNX are provided.

In the memory protection buffer MGB, the upper limit address and lower limit address of the main memory unit MMU used by each operating system are stored by the host operating system that controls all operating systems, and the data DTAM is stored from the control memory unit CMU in accordance with the operating system. is supplied and written as.

The operating system at this time is specified by the identifier SIDM from the control memory unit CMU.

The switch MXI accepts one of the memory requests REQM and REQD from the control memory unit CMU and the channel data unit CDU (in case of conflict, the request REQD is given priority), and sends the request to the control circuit C0NT. Output. Control circuit C
0NT is the memory request REQ from the switch MXI
M or RE Q D &,: In response, switch MX2
．． MX3゜MX4. A switching signal (not shown) is generated and supplied to each of MX5 and MX6 to allow the corresponding data from the control memory unit CMU or the channel data unit CDU to be accepted. That is, the switch MX2 has the identifier SIDM or 51DD, the switch MX3 has the address ADRM or ADRD, and the switch M
X4 is request code RQCM or RQCD, switch MX5 is sea yZONM or ZOND, switch MX
6 accepts either data DTAM or DTAD in response to the above switching signal.

Switcher MX2. MX3. MX4. The identifier SID, address ADH, request code RQC, zone ZON and data DTA received by MX5 and MX6 are respectively identifier register 5IDR and address register A.
DRR, request code register RQCR, zone register ZONR, and data register DTAR are held.

Address ADH, request code RQC, zone ZO
N and data DTA are supplied to the system control unit (SCU) and used to access the main memory MMU. However, the zone ZON specifies the write byte position in one memory word during a partial write operation, and if this write byte position specification specifies all zeros, even if the write operation is instructed by a request code, the main memory MMU Since data DTA is data that should be written to the address specified by address ADR in main memory MMU, request code RQCM or RQ CD
IJ<When a read operation is specified, each original data zone ZONM,
ZOND and data DTAM and DTAD are not supplied and are considered invalid in the system control unit SCU.

91 changer ZNX is the system control unit)
Either give the output of the zone register ZONH as the write byte position specification (zone) to the SCU or all zeros (
(no write bytes).

Now, the control memory unit CMU or channel data unit CDU outputs a memory request REQM or REQD, an identifier SIDM or 5IDD, etc., respectively based on an input/output command, and outputs a memory request REQM or REQD, an identifier SIDM or 5IDD, etc.
When trying to access the identifier register 5ID
The identifier SID held in R is the memory protection buffer MG.
Used as an address for reading B. As mentioned above, the memory protection buffer MGB has the identifier SI.
Since the upper limit address and lower limit address of the main memory bag WMMU used under the operating system associated with D are stored, they are read out to the comparators C0M1 and C0M2, respectively.

On the other hand, the address register ADRR holds an address ADH generated from a program under the same operating system as the identifier SID used to access the memory protection buffer MGB at this time. As described above, this address ADH is the same as the absolute address obtained as a result of address conversion of the virtual address on the program by the arithmetic processing unit EPU.

The upper bit of address ADH that defines the memory area is supplied to comparators C0M1 and C0M2, and comparator COMI checks whether the value determined by this upper bit does not exceed the upper limit address. It is checked whether the value determined by the upper bits is smaller than the lower limit address. When the comparator COMI finds that the upper limit address is exceeded, the comparator C0M1 outputs "1", and when the comparator COM2 finds that it is smaller than the lower limit address, the comparator C0M1 outputs "1".
M2 outputs "1".

Based on this result, the NOR gate NOR outputs “O”,
Controls the switch ZNX and controls the system control unit/
) Forcibly change the write byte position designation (zone) given to SCU to all zeros.

In the embodiment described above, address conversion from a virtual address to an absolute address is performed by the arithmetic processing unit EPU.
However, this is not intended to limit the present invention, and the control memory unit CMU of the input/output processing device 10P may be used as in a large-sized computer.

〔Effect of the invention〕

As explained above, by employing the above configuration, the present invention prevents destruction of other operating system areas due to software malfunction even in a virtual input/output processing device that can obtain absolute addresses as address translation results. It has a deterrent effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing the hardware environment of this embodiment. In the figure, ADRR: Address register, C0M1. C0
M2... Comparator, C0NT... Control circuit, DTAR... Data register, MGB... Memory protection buffer, MXI, MX2
．． MX3. MX4. MX5'. MX6. ZNX...Switcher, NOR...Noah gate, RQCR...Request code register, 5ID
R: Identifier register, ZONR: Zone register. Figure 2 Figure 3 Go to SCU

Claims (1)

[Scope of Claims] A virtual input/output processing device that controls data transfer between a peripheral device and a main storage device according to each input/output command from a plurality of operating systems, and obtains an absolute address as an address conversion result. In the memory protection method, an address area storage means for storing in advance an upper limit address value and a lower limit address value defining an area on the main storage device used by each of the operating systems corresponding to the operating system; an address information holding unit that holds address information associated with an access request from a virtual input/output processing device to the main storage device; and a zone holding unit that holds a write byte position specification to the main storage device that corresponds to the access request. means, an identifier holding means for holding a program identifier of an operating system to which the input/output instruction that generated the access request belongs; a reading means for reading the address area storage means using this program identifier; address comparison means for comparing the address information with an upper limit address value and a lower address limit value; A memory protection method comprising: switching means for permitting the access request when the area is within the area, and forcibly changing the output of the zone holding means to specify no write bytes when the area is outside the area.