JPS6257042A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the efficiency at program execution of a CPU while plural physical addresses are designated alternatively to one logic address input by providing an internal address conversion circuit. CONSTITUTION:A semiconductor memory 10 and a CPU are connected by an address bus 3 and a data bus 4, and an input address from the bus 3 is inputted to the internal address conversion circuit 11, where the address is converted into an internal address and outputted from the internal address bus 12. Further, the circuit 11 has an exclusive OR circuit 21 and a storage element 22 corresponding at least to 1 bit of the address input. That is, a bit signal Ai of the address input and a storage data Xi of the element 22 are inputted to the circuit 21 and an output signal Ai' of the circuit 21 is used as the bit signal of the internal address. Then, the storage data in the element 22 is operated externally. Thus, the conversion is attained in a way to designate alternatively plural physical addresses to one logic address input and the efficiency is improved in the program execution by the CPU.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor memory realized as a memory integrated circuit or an on-chip memory, and in particular, the present invention relates to a semiconductor memory realized as a memory integrated circuit or an on-chip memory, and in particular, a programmable address function that converts an input address to an internal address according to predetermined control data. The present invention relates to a memory having an address conversion section for converting the address into an address for use.

[Technical background of the invention]

In a conventional semiconductor memory, when an input address is given from a CPU (central processing unit), an internal address is uniquely determined, and data at this internal address is read out or stored at the internal address. That is,
There is a one-to-one correspondence between the input logical address and the physical address of the memory cell to which reading and writing are actually performed. Therefore, when CPU J and memory 2 are connected by address bus 3 and data bus 4 as shown in FIG. 9, a certain address area (block If there is a program that performs a certain operation on block A, the CPU specifies the logical address of block A and executes the program. Here, when executing the above program on another block B, first transfer the data of block B to the area of block A, execute the program on the program area, and then transfer the data of block A to block B. It is necessary to transfer and store it in the area. In other words, the flowchart of data processing in this case is as shown in FIG. In addition, as is well known, the subroutines for block transfer include specifying the start address of the transfer source block, specifying the transfer address of the transfer destination block, setting the number of transfer data (number of bytes), and transferring each data transfer. A series of processes including decreasing the number of remaining data, incrementing the transfer source address, and incrementing the transfer destination address are repeated until the number of remaining transfer data becomes zero.

[Problems with background technology]

As mentioned above, in conventional memory, when a CPU executes a program that involves data transfer between two blocks A and B in the address space, data is transferred every time the program is executed. When there is a large amount of data to be transferred, there is a problem in that the program execution time becomes long. In addition, when executing a program that involves data transfer between three or more blocks, the 11th
Since the number of execution loops in the flowchart shown in the figure increases, the program execution time also increases.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to convert one logical address input so that multiple physical addresses are alternatively specified, and it is possible to efficiently execute a program by a CPU. The purpose is to provide a semiconductor memory that enables

[Summary of the invention]

That is, in the semiconductor memory of the present invention, an input address is input to an internal address conversion circuit and is converted into an internal address for specifying a physical address in an address space, and the internal address conversion circuit is capable of changing settings of stored data. The present invention is characterized in that at least one bit of an input address is inverted or not inverted according to data stored in a possible storage element.

With this, it is possible to selectively specify a plurality of physical addresses for one logical address input according to the storage data of the storage element, and the storage element data setting can be performed as a CPU program instead of, for example, a block transfer routine. This makes it possible to reduce the number of program steps and improve the efficiency of program execution.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, 10 is a semiconductor memory, and an address bus (external address bus) 3 and a data bus 4 are connected to the CPU. Inside the memory 10, an input address from the address bus 3 is input to an internal address conversion circuit 11 via an address buffer (not shown), where it is converted into an internal address, and this internal address is transferred to an internal address bus 12. The data is supplied to an address decoder (not shown) or the like through the address decoder (not shown).

The internal address conversion circuit 1 has an exclusive OR circuit 2 and a memory element 22, as shown in FIG. 2, corresponding to at least one bit (in this example, each bit) of the address input. That is, the address input bit signal Ai and the storage data x1 of the storage element 22 are input to the exclusive OR circuit 21, and the output signal Al' of the OR circuit 21 is used as the internal address bit signal. . The data stored in the storage element 22 can be manipulated from outside the memory.

That is, for the memory element 22, a flip-flop circuit as shown in FIG. 3 is used, for example. That is, 3 and 32 are two-input NOR circuits, 33 and 34 are N-channel transistors, and 35 and 36 are inverter circuits, and when setting the input data Xi, the latch enable signal φKl is set to the attenuated state ("Os level"). You can return it to the inactive state later.For example, X, = @
l' and φ■ to @Oa, the output of the NOR circuit 3 is 10 m, the transistor 33 is off, and the NOR circuit 32 is
The output is "1m, 1m, 34 transistors, the input to the inverter circuit 350 is @O# (V, 8 potential, ground potential), and the output xi is "1". On the contrary, xi
= @o” and φLE is “0”, NOR circuit 3
The output of the NOR circuit 32 is "1", the transistor 33 is on, the output of the NOR circuit 32 is @O", the transistor 34 is off, and the input Xl of the inverter circuit 36 is "01".

According to the internal address change circuit 12, when looking at each bit of the address, as shown in FIG. 1" (internal address bit Al' is left as Ai, storage data x1 is
If it is 1m, address input bit Ai @QJI
. Therefore, for example, a 2-pit logical address input Ao+
2-pit storage data for AI x6. The internal addresses (physical addresses) that can be converted by XH are as shown in FIG. That is, stored data XQ.

Address input A11eA when xl is O#, ″″0#
1, 4 letters, bo changes (''O'', 'O'), (-0
”, “l”).

Assuming that physical addresses A, B, C, and D are specified corresponding to (@1", "0") and ("1", "1'), storage data XQ is set to "1". Te (xo * xt)
By setting = (-1″, ″0″), the Ao-bit of the address input is inverted, so the address input Ao
-As O Due to the above four changes, A and C among the specified physical addresses are interchanged. Also,
Set the stored data x1 to ″11 and (xo, xl)=(
``O'', @l') to input the address A.
Since the I pit is inverted, the address input AOe Al
Among the specified physical addresses, A and B and C and D are exchanged due to the above four changes. Also, set the stored data 10eXt to “1” (xl)sXl)=(″
1", @l"), the address input AO
*Since the A1 pit is also inverted, the address input AOe
Among the physical addresses specified by the above four changes in A1, A and D and B and C are exchanged.

Note that the address inputs AO, A in the above address conversion
If 1 is, for example, the upper two pits of the 16-pit address input, physical addresses A, B, C, and D each correspond to an address area (block) with a size of 2-16384=4FFF(H).

That is, according to the memory having the above-mentioned internal address conversion circuit J2, the CPU executes the data transfer, program execution, and data storage processing routines for the two blocks A and H of the memory area as shown in the conventional example. Instead of a program that repeats the steps (see Figure 11), use a simple program that keeps the logical address input constant and repeats the routine of setting storage data in the storage element and executing the program as shown in Figure 6. This improves program execution efficiency. In addition, regarding the transfer of block data, conventional methods include setting the transfer source address, setting the number of transfer data, setting the transfer destination address, and setting the transfer data count.
Although it is necessary to include zologram steps such as counting 0 and determining whether there is any remaining data to be transferred, according to this embodiment, the desired result can be achieved with a short program step that only sets the storage data in the storage element. It is possible to specify the physical address where block data exists without depending on the number of transferred data, and it is possible to improve the efficiency of program execution.

In addition, in the above explanation, a case was shown in which a program was executed that specified absolute addresses as the physical addresses of two blocks A and B, but as shown in FIG. Block Ai +
When executing a program on the data of Am m...An, all you have to do is repeat the processing routine of setting the stored data, executing the program, and incrementing the address. It is no longer necessary to add an absolute address and a relative address or to specify an absolute address, and it is possible to improve the efficiency of program execution.

Furthermore, according to this embodiment, when accessing block A of the address space as shown in FIG. By changing the settings, it is possible to access the entire block including block A and area C.

Note that as the memory element 22 in the above embodiment, various circuits may be used instead of the Frizzo-Frodde circuit. For example, when a double signal φ is input, charging and discharging of a capacitor may be controlled according to the logic level of input data X1, and the terminal voltage of this capacitor may be latched by a latch circuit. Alternatively, if the input data Xi is stored in a memory cell of an electrically erasable/rewritable non-volatile memory (I PROM) when the φ and double signals are input, the data can be stored even after the main power supply is cut off. Since the stored data is retained, there is no need to initialize the stored data when the memory is usable. For the same reason, if the writing frequency of the stored data may be low, the stored data may be set in a memory of an ultraviolet erasable/rewritable non-volatile memory (IPROM).

〔Effect of the invention〕

As described above, according to the semiconductor memory of the present invention, it is possible to convert one logical address input so that a plurality of physical addresses are alternatively specified, and the program can be executed efficiently by the CPU. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing the main part of the semiconductor memory of the present invention, FIG. 2 is a configuration explanatory diagram showing 1 bit of the internal address conversion circuit in FIG. 1, and FIG. A circuit diagram showing an example of a memory element, FIG. 4 is a truth table of the circuit in FIG. 2, and FIG. 5 shows an internal address conversion operation for the upper two bits of an input address by the internal address conversion circuit in FIG. The truth table and WXG diagram shown in Figure 1 are created using the memory shown in Figure 1.
1 is a flowchart for performing processing equivalent to the conventional memory processing shown in FIG. 1, and FIG. 7 is a diagram showing block positions in the address space and a flowchart to explain an example of processing performed using the memory in FIG. 1. ,
FIG. 8 is a diagram showing block positions in the address space to explain another example of processing performed using the memory shown in FIG. 1, FIG. 9 is a diagram showing an example of connection between the memory and the CPU, and FIG. and FIG. 11 is a diagram showing block positions in an address space and a flowchart for explaining an example of processing performed using a conventional memory. 3...Address bus, 4...Data bus, 10...
・Semiconductor memory, 11... Internal address conversion circuit, 1
2...Internal address/4th, 2...Exclusive OR circuit, 22...Storage element. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 3 Figure 4 Figure 5 Figure 8 Figure 7

Claims (5)

[Claims] (1) An input address is input to an internal address conversion circuit and converted into an internal address for specifying a physical address in the address space, and the internal address conversion circuit is a memory element that can change the settings of stored data. A semiconductor memory characterized in that it is configured to invert or not invert at least one bit of an input address according to data. (2) The storage element is provided corresponding to each bit of the input address, and inversion/non-inversion control for each bit of the input address is performed on a bit-by-bit basis according to the data stored in each storage element. A semiconductor memory according to claim 1, characterized in that: (3) The internal address conversion circuit is formed by using an exclusive OR circuit having two inputs: bits of an input address and data stored in a storage element. semiconductor memory. (4) The semiconductor memory according to claim 1, wherein the memory element is a flip-flop circuit. (5) The semiconductor memory according to claim 1, wherein the memory element is a nonvolatile memory element.