JPS6256599B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention changes the potential state of a pair of data lines holding different potentials from a first potential state to a second potential state.
The present invention relates to a data line potential setting circuit for transitioning to a potential state of , and an MIS memory circuit using the same.

In general, in an insulated gate transistor memory circuit (hereinafter simply referred to as an MIS memory circuit) in which writing and reading are performed via a pair of common data lines, the potential state of the common data line (first It is necessary to shift the potential state (potential state) to the potential state (second potential state) required at the time of reading, and a data line potential setting circuit is used to shorten the time.

MIS using such a data line potential setting circuit
The memory circuit will be explained with reference to FIG.

In the same figure, 1 is a memory cell MS ₁₁ ~ _{MS no}
This is a memory matrix in which data is arranged in m rows and n columns. Reference numeral 2 denotes a row selection address decoder which selects each row of the memory matrix using row address signals W ₁ to W _n . 3 connects a pair of digital lines D ₀₁ , D ₁₁ to D _po , D _1o arranged in each column to a common common data line.
It is a column gate means for connecting to CD ₀ -CD ₁ and has a pair of column gate switching elements Q ₅ , Q ₆ -Q ₅ ', Q ₆ ' for each column. 4 is the pair of column gate switching elements Q ₅ , Q ₆ .
This is a column selection address decoder that selects Q ₅ ′ and Q ₆ ′ using column gate signals CL ₁ to _{CL o} . 5 is a load means for supplying current to a pair of digit lines D ₀₁ , D ₁₁ to _{D 0o} , D _1o in each column;
It consists of MISFETQ ₇ , Q ₈ to Q ₇ ′, and Q ₈ ′. 6 is CSX
signal, WED signal, WE′ signal,
This is a write circuit for amplifying write data from the input/output terminal I/O and transmitting the amplified data to the pair of common data lines. 7 is CSX signal, WE signal,
”Controlled by signal, common data line
This is a readout circuit that amplifies the data read out to CD ₀ and CD ₁ and transmits it to the input/output terminal I/O. 8
is a data line potential setting circuit connected to a pair of common data lines, and MISFETQ ₉ ′, Q ₉ are connected between the common data line CD ₀ and the bias source V _CC ,
The circuit has a circuit configuration in which MISFETQ ₁₀ ′ and Q 10 are connected between the common data line CD ₁ and the bias source V _CC , and the MISFETQ ₉ and _{Q 10 are} controlled by the ″ signal. Each memory cell is MS ₁₁ ,
MISFETQ ₃ cross-connected as shown in MS _no .
Q ₄ , Q ₃ ′, Q ₄ ′ and their cross connection points A, B, A′,
MISFETs _{Q 1} , Q 2 , Q _{1 '} , Q _{2 '} are connected between B' and the digital lines D ₀₁ , D ₁₁ , D _0o , D _1o and to which row address signals W ₁ to _{W n} are applied. , bias source V _C
C and the load elements R ₁ , R ₂ , R 1 ', R ₂ ' connected between the cross connection points A, B, A _' , B', and one of the cross connection points to a high level (hereinafter,
It is called H level. ) has a function of statically storing and holding data so that a low level (hereinafter referred to as L level) is generated at the other cross-connection point. Further, as shown in FIG. 2, the write circuit 6 includes a push-pull amplification stage consisting of MISFETs _{Q 42} , Q ₄₃ , Q ₄₉ , Q ₅₀ , and Q ₅₆ , the push-pull amplification means, and a pair of common data lines CD ₀ and CD ₁ . A transmission means consisting of MISFETQ ₄₂ ′ and Q ₄₉ ′ connected between them, a first inverter waveform shaping means consisting of MISFETQ ₄₄ , Q ₄₅ , Q ₅₁ , Q ₅₂ , Q ₅₇ , and MISFETQ ₄₆ ,
The second inverter waveform shaping means includes Q ₄₇ , Q ₅₃ , Q ₅₄ , and Q ₅₈ , and the input buffer means includes MISFETs Q ₄₈ , Q ₅₅ , and Q ₅₉ . amplification means
By controlling the WED signal and the first and second inverter waveform shaping means and input buffer means using the CSX signal, write data from the input/output terminals is amplified and transferred to the pair of common data lines.
Apply to CD ₀ and CD ₁ .

Note that when the bias source V _CC is 4.5V, the level of the write data transmitted to the common data line is 3.8V (H) level, and the other is 3.8V (H) level.
This is the “L” level of 0.3V. Also, the above
MISFETQ ₄₄ ~ Q ₄₈ are depletion type,
Others are enhancement types.

Further _, as shown in _{FIG .} 3, the readout circuit 7 has _a first
a first differential amplifying means drive control means _{consisting of MISFETQ 62} , Q _{63 ,} and _{Q 76 ;} 2 differential amplification means and MISFETQ ₆₆ ,
A second differential amplification drive level control means consisting of Q ₆₇ , Q ₈₁ and MISFETQ ₈₂ , Q ₈₄ , Q ₆₈ ,
A first push-pull amplification means consisting of _Q83 , _Q85, and a second push-pull amplification means consisting of _MISFETQ86 , _Q70 , _Q87 , _Q71 .
Push-pull amplification means, MISFETQ ₉₀ , Q ₉₁
It is composed of a TTL signal level driving inverter means consisting of a TTL signal level drive inverter means and a tri-state means consisting of MISFETQ ₈₉ and Q ₈₉ ', and a first and second differential amplification means and a first and second differential amplification means drive The level control means for the first and second
By controlling the push-pull amplifying means ``signal'' and the tri-state means using the _WE1 signal, the data read out to the common data lines CD ₀ and CD ₁ is amplified and taken out to the input/output terminal.

Note that the optimal level of the signal applied to the first differential amplification stage is when the bias source V _CC is 4.5V.
One is 3.8V “H” level, the other is 3.5V
is at the "L" level, and the level difference is about 0.3V. Furthermore, the above MISFETs Q ₆₀ to _{Q 71} are of the depletion type, and the other MISFETs are of the enhancement type.

In the MIS memory circuit shown in FIG. 1 having the above configuration, suppose that data is written to the memory cell MS ₁₁ and immediately thereafter data is read from the memory cell MS _no in the same chip _. The potential state (first potential state) when writing ₁ is the potential state (second potential state) required during reading.
How the voltage is shifted to the potential state) will be explained with reference to the timing chart of FIG.

In addition, in the same figure, signal, signal, Ai
The signal, Din/D _OUT , is applied from outside the IC chip, and the other signals are generated inside the IC chip.

When the signal becomes "L" level at timing _t1 , the chip is selected, and an external address signal Ai is applied to the 1st row and column selection address decoders. Thereby, memory cell _MS11 is selected, and digital lines _D01 and _D11 are connected to a pair of common data lines _CD0 and _CD1 via column gate switching elements _Q5 and _Q6 . Furthermore, since MISFETQ ₁ and Q ₂ are also ON, the cross-connection points A and B are connected to the pair of digital lines D ₀₁ and D ₁₁ .

At timing _t2 , since the WE' signal is at the "L" level, the write circuit 6 in FIG. 1,2
The inverter waveform shaping means and the input buffer means are each in operation, thereby amplifying the write data DiN applied from the input/output terminal and transmitting the amplified data to the pair of common data lines CD ₀ and CD ₁ .

Now, when DiN is set to "H" level, the potential of the common data line CD ₀ becomes "H" level (V _1H ) of about 3.8V, and the potential of the common data line CD ₁ becomes about _3.8V (V _1H ). It becomes “L” level (V _1L ) of 0.3V. The levels of V _1H and V _1L indicate the first potential state.

The first potential states V _1H and V _1L of the pair of common data lines CD ₀ and CD ₁ are column switching means.
Q ₅ , Q ₆ and a pair of digit wires D ₀₁ , D ₁₁ and
It is also transmitted to the cross-connection points A and B of the memory cell MS ₁₁ via the MISFETs Q ₁ and Q ₂ .

Now the load means of memory cell MS ₁₁ MISFETQ ₇ ,
Since the current driving ability of Q ₈ and the load resistance elements R ₁ and R ₂ is smaller than the current driving ability of the push-pull amplification means of the write circuit 6, the levels of the cross-connection points A and B become V _1H and V _1L . Furthermore, at this point, the V _1H and V _1L are also accumulated in the parasitic capacitances C ₀ and C ₁ existing on the common data lines CD ₀ and CD ₁ .
Note that a plurality of pairs of digit lines D ₀₁ , D ₁₁ to _{D 0o} ,
Since the common data lines CD ₀ and CD ₁ are commonly used for D _1o , their line lengths are long, and therefore the parasitic capacitances C ₀ and C ₁ are very large.

At timing _t3 , the "L" level of the WE' signal is applied to the transmission means of the write circuit 6, so the common data lines _CD0 and _CD1 are connected to the write circuit 6.
Although electrically disconnected from the capacitance
The level is maintained at the first potential state by C ₀ and C ₁ .

At this point, the load means Q ₇ , Q ₈ and the load resistance elements R ₁ , R ₂ can supply bias to the cross-connection points A and B without being restricted by the push-pull amplification means of the write circuit 6. becomes.
In addition, when the signal " becomes "H" level, the data line potential setting circuit 8 also starts operating.

Of the data line potential setting circuit 8
Since the common data line _CD0 of _MISFETQ9 ' and _Q9 is _V1H , the potential difference between their gates and sources is less than the threshold voltage (approximately 0.7V), so they are each turned off. Also, MISFETQ ₁₀ ′, Q ₁₀ is the common data line CD ₁
Since the voltage is V _1L , the potential difference between the gate and source is higher than the threshold potential (approximately 0.7V), so each of them is turned on. As a result, the capacitor _C1 is charged via _MISFETQ10 ' and _Q10 , and the level of the common data line _CD1 is gradually raised.

On the other hand, the cross-connection point A of the memory cell MS ₁₁ operates so as to change from the above V _1L to V _2H , a level determined by the load means Q ₇ and the MISFETs _{Q 1} and Q ₃ . Further, the cross-connection point B remains at V _2H at the time of writing.

Further, since the current driving capability of the load means _{Q 7 and} Q ⁸ of the memory cell MS 11 is larger than that of the data line potential setting circuit 8, the level of the common data line is set at the cross connection points A and B of the memory cell MS ₁₁ . It is fixed at the level determined by . Accordingly, in Figure 4
During the period indicated by _T1 , the level of common data line _{CD1 is VCD.
1} changes from V _1L to V _2L , and the level of the common data line CD ₀ changes from V _1H to V _2H , which is substantially the same potential, and the level difference is about 0.3V.

It would be possible to switch the address signal Ai to select the next memory cell MS _no when the level difference of the common data lines reaches about 0.3V, but in reality there is a slight delay and the switch is switched at timing _t5. It will be done. From timing _t4 to timing _t5 , the levels of the common data lines _CD0 and _CD1 are each held at the second potential state.

At timing _t5 , when address signal Ai switches, memory cell MS _no is selected, thereby causing common data lines _CD0 and _CD1 to be connected to a pair of data lines through column gate switching elements _Q5 ' and _Q6 '. It is connected to the digital lines D _0o and D _1o . Now, at the cross-connection point A′ of the memory cell MS _no , there is a load means Q ₇ ′,
Potential V _2H determined by MISFETQ ₁ ′, Q ₃ ′
However, B′ also has load means Q ₈ ′, MISFETQ ₂ ′,
A potential V _2L determined by Q ₄ ' exists, and data opposite to the data written in the memory cell MS ₁₁ is stored and held. Therefore, memory cell MS _no inverts the levels of common data lines CD ₀ and CD ₁ from V _2H and V _2L to V _2L and V _2H .

At timing t ₃ , common data lines CD ₀ ,
The potential states V _2L and V _2H necessary to read the data of memory cell MS _no to CD ₁ , that is, V _2L is 3.5V,
When V _2H reaches 3.8, the read circuit 7 amplifies the level difference of 0.3 V between the common data lines CD ₀ and CD ₁ in an optimal state, and reads read data D _OUT from the input/output terminal I/O. In this case, read data D _O
UT is at "L" level. Note that at timing _t6 , the readout circuit 7 is operational because the CSX signal is at the "H" level and the _WE1 signal is at the "L" level.

The operation of the MIS memory circuit shown in FIG. 1 has been described above, and by using the data line potential setting circuit 8 in the same drawing, the write recovery time can be shortened. However, at present, there is a demand in the market to further shorten the write recovery time.
It has become necessary to satisfy the specifications.

Therefore, an object of the present invention is to provide a data line potential setting circuit that can more rapidly obtain a level difference between second potential states.

Another object of the present invention is to provide a data line potential setting circuit that can obtain a level difference between the second potential state at a position closer to the second potential state.

Furthermore, it is an object of the present invention to provide a data line potential setting circuit that does not supply current when the potential state of a pair of data lines approaches the second potential state.

Furthermore, it is an object of the present invention to provide a data line potential setting circuit that can clamp the level of a pair of data lines near the second potential state when the potential state of the pair of data lines approaches the second potential state. .

Although the basic constituent elements of the present invention are as described in the claims, the present invention will be explained in detail below with reference to Examples.

FIG. 5 shows an MIS memory circuit using the data line potential setting circuit 9 according to the present invention.
The first example except that a data line potential setting circuit 9 according to the present invention is used instead of the data line potential setting circuit 8, and a write recovery signal generating circuit 10 is added.
Its configuration is the same as the MIS circuit shown in the figure. 1st
The same numbers and symbols are used for parts common to the figures. Further, since the explanation of these common parts has already been mentioned above, the explanation will be omitted here.

In FIG. 5, the readout circuit 7' has the same circuit configuration as the readout circuit 7 used in the MIS memory circuit of FIG. 1, but as will be described later, the readout circuit 7' is The readout levels "H" level and "L" level are lower values than in the conventional case. (For example, if the bias source is 4.5V, the optimal values for “H” level and “L” level are
2.8V, 2.5V. ) Further, each cross-connection point of each memory cell is at the "H" level when it matches the optimum level for reading in the storage state, and the other is at the "L" level.

In FIG. 5 above, the data line potential setting circuit 9 according to the present invention is connected between the common data lines.
switching means 9' consisting of MISFETQ ₁₁ ;
Current supply means 9″ consisting of MISFETQ ₉ and Q ₁₀ connected between bias source V _CC and each common data line
and a clamping means 9 consisting of depletion type MISFETs Q ₁₂ and Q ₁₃ and enhancement type MISFETs _{Q 14} to Q ₂₀ .

The write recovery signal generation circuit 10 includes CSA ₁ and WED shown in the timing chart of FIG.
A first write recovery signal φ _WR1 and a second write recovery signal φ _WR2 are generated by being controlled by the signal.

The switching means 9' is controlled by the first write recovery signal _φWR1 .
MISFETQ ₁₁ operates in the non-saturation region.

The current supply means 9'' is controlled by the second write recovery signal _φWR2 ,
MISFETQ ₉ and Q ₁₀ operate in the saturation region.

In the clamping means 9, MISFETQ ₁₈
are controlled by the WE signal shown in the timing chart of FIG. 7, MISFETQ ₁₉ is controlled by the CSA ₂ signal, and MISFETQ ₂₀ is connected to the bias source V _CC , so MISFETQ ₁₈ to _{Q 20}
means converts the level of the bias source V _CC ,
Apply that voltage to _MISFETQ16 - _Q17 .
MISFETQ ₁₃ and Q ₁₄ are each controlled by the WE' signal. Therefore, MISFETQ ₁₃ , Q ₁₅ ,
The means consisting of Q ₁₇ and the means consisting of MISFETs _{Q 12} , Q ₁₄ and Q ₁₆ respectively bring the common data lines CD ₀ and CD ₁ to the intermediate level of the second potential state of V _2L and V _2H .

Note that FIG. 6 shows a specific circuit diagram of the write recovery signal generation circuit 10.

In the figure, MISFETQ ₂₁ to _{Q 27} are depletion type MISFETs, and MISFETQ ₂₈ to _{Q 41} and Q ₂₉ ′, Q ₃₀ ′ are enhancement type MISFETs.
It is MISFET.

MISFETQ ₂₁ , Q ₂₃ is the first inverter, the WED signal is applied to its input, and the output is P ₁
It is. MISFETQ ₂₉ ′, Q ₂₂ , Q ₂₀ is the second inverter, to whose input P ₁ is applied, and the output is
It is _P2 .

In addition, for MISFETQ ₂₉ ′, CSA ₁ is used for MISFETQ ₂₅ ,
A signal P ₅ inverted at Q ₃₄ is applied.
MISFETQ ₃₀ ′, Q ₂₃ , Q ₃₀ is a third inverter to which P ₂ is applied and the output is P ₃ .

In addition, for MISFETQ ₃₀ ′, CSA ₁ is used for MISFETQ ₂₅ ,
A signal P ₅ inverted at Q ₃₄ is applied.

MISFETQ ₂₄ , Q ₃₂ is a fourth inverter, the input of which is determined by the signal of P ₃ and the output of MISFETQ ₃₁ receiving the CSA ₁ signal, the output of which is P ₄ and the second inverter Recovery signal φ
Connected to the output terminal of _WR2 .

Note that P ₄ is MISFETQ ₃₃ that receives the WED signal.
It is also controlled by.

MISFETQ ₂₆ and Q ₃₅ are the first delay means,
P ₃ is applied to its input and its output is P ₆ .

MISFETQ ₃₆ and Q ₃₇ are second delay means,
MISFETQ ₃₆ has the above P ₆ , MISFETQ ₃₇ has P ₃
are applied respectively, and the output is _P7 . Said _P7 is also controlled by MISFETQ ₃₆ which receives the WED signal.

MISFETQ ₂₇ , Q ₃₉ is the fifth inverter, which receives P ₇ as its input and has P ₈ as its output.

_MISFETQ40 , _Q41 and capacitor CB are boost strap means, and _P8 is applied to _MISFETQ41 . In addition, a bootstrap capacitor CB is connected between the gate and source of MISFETQ ₄₀ .
P ₇ on one charge and on the other electrode
Earth level via MISFETQ ₄₁ or
V _CC is applied through _MISFETQ40 . A first write recovery signal _φWR1 is taken out from one electrode of the capacitor CB.

The operation of the write recovery signal generation circuit 10 will be briefly explained.

First, when CSA ₁ is at the "H" level and WED is at the "H" level, _P1 is at the "L" level, _P2 is in the oven state, _P3 is at the "L" level, and _P4 is at the "L" level. Therefore, the second write recovery signal is at "L" level, _P6 is at "H" level, _P7 is at "L" level, _P8 is at "H" level, and _P9 is at "L" level. Since the first write recovery signal is at the "L" level, the first write recovery signal is also at the "L" level.

Next, CSA ₁ goes to “L” level and WED goes to “H”
When _P1 is at the "L" level, _P2 is at the "H" level, _P3 is at the "L" level, and _P4 is at the "L" level, so the second write recovery signal φ _WR
2 is the "L" level. Also, since _P6 is at the "H" level, _P7 is at the "L" level, _P8 is at the "H" level, and _P9 is at the "L" level, the first write recovery signal _φWR1 is also at the "L" level. be.

Furthermore, when CSA ₁ becomes "L" level and WED becomes "L" level, P ₁ becomes "H" level, P ₂ becomes "L" level, P ₃ becomes "H" level, and P ₄ becomes " However, since the WED signal is delayed by the first, second, and third inverters, the level of _P4 is initially “H” level, and the second
The write recovery signal φ _WR2 generates a level of approximately V _CC .

When the level of P ₃ becomes "H" level, the level of P ₄ becomes "L" level, so at that point, the second write recovery φ _WR2 signal changes to "L" level. That is, at the time when WED becomes "L" level, the second write recovery signal φ _WR
2 generates a one-shot "H" level.

When _P3 is still at the "L" level, _R6 is at the "H" level and _P7 is at the "H" level. _P8 is _P7
It goes to “L” level _in response _to
A current flows through the capacitor CB, and charge is supplied to the capacitor CB.

Next, when P ₃ becomes completely "L" level
Since MISFETQ ₄₁ is turned off, the level of _P9 becomes V _CC . As a result, the capacitance CB is bootstrapped, and one electrode has a high “H” of approximately 2·V _CC −V _th .
level as the first write recovery signal _φWR1 .

Next, when the level of P ₃ becomes completely "H" level, P ₆ becomes "L" level and P ₇ becomes "L" level, so that the first write recovery signal φ _WR1 becomes It becomes “L” level.

Therefore, the first write recovery signal φ _WR
1 outputs a one-shot "H" level from the time the WED signal becomes "L" level.

The configurations of the data line potential setting circuit 9 and the write recovery signal generating circuit 10 according to the present invention in the MIS memory circuit shown in FIG. 5 have been explained above.
When using , the first potential state at the time of writing is
The operation of how quickly the second potential state necessary for reading is made will be explained with reference to the timing chart of FIG. 7.

In the MIS memory circuit shown in FIG. 5, first, the "H" level of D _iN is written to the memory cell MS ₁₁ , and immediately after that, D _{OUT is} written from the memory cell MS _no in the same chip.
Assume that the "L" level is read out.

Therefore, since the conditions are the same as those of the MIS memory circuit of FIG. 1, the explanation will be given from timing _t3 in the timing chart of FIG. 7. In Fig. 7, the CS signal, WE signal, Ai signal, and D _IN /D _OUT each indicate a signal taken in from outside the IC chip or a signal taken out to the outside, and other signals are internal to the IC chip. It was formed.

At timing _t3 , the WE' signal goes to "L" level, so that the write circuit 6 is electrically disconnected from the common data lines _CD0 and _CD1 . However, the capacitance of common data lines CD ₀ and CD ₁
C ₀ and C ₁ have respective potential states at the time of writing, that is, V _1H and V _1L .

At this point, since the CSA2 and WED signals are both at the "L" level, the write recovery signal generating circuit 10 has a potential of approximately the bias source V _CC (indicated by V _WR2 in FIG. 7). ) a second write recovery signal φ _WR2 and a first write recovery signal φ _WR1 having a voltage of about 2·Vcc−V _th (indicated by V _WR1 in FIG. 7), respectively.

Thereby, first of all, the switching means 9'
MISFETQ ₁₁ electrically connects common data lines CD ₀ and CD ₁ , so the charge of capacitor C _{0 is}
are discharged to the capacitor C1 through the capacitor _C1 , causing charge dispersion with each other. As a result, the level of the common data line CD ₀ decreases, and the level of the common data line CD ₁ increases. Note that this rise and fall are performed with almost the same characteristics.

In addition, since the first write recovery signal φ _WR1 of MISFETQ ₁₁ is 2·V _cc −V _th , approximately 8.3V, the non-conformity indicated by Z ₁ in the output voltage-output current characteristics of MISFET shown in FIG. Since it operates in the saturation region, its operating resistance is extremely small.

Therefore, the fall of the level of the common data line CD ₀ and the fall of the level of the common data line CD ₁ are steep, and the common data line
CD ₀ and CD ₁ rapidly approach near the second potential state from the first potential state.

Furthermore, since the second write recovery signal φ _WR2 is applied to the current supply means 9″, the MISFETQ ₁₀
is ON, and MISFETQ ₉ is connected to the common data line CD ₀ .
It is off because it is at V _1H of 3.8V. MISFETQ ₁₀
Since charge is supplied to the capacitor _C1 from the common data line by the switching means 9',
It will help you build up your level for CD ₁ .

Therefore, the level difference in the second potential state can be obtained earlier.

Therefore, at timing _t4 , the common data lines CD ₀ and CD ₁ are in the first potential state V _1H and V _1L
to V _2H ′, V _2L ′ near the second potential state,
(In this second potential state, V _2H ′, V _2L ′
Both values are lower than in the conventional case. ) The level difference is also about 0.3V.

At this point, it would be ideal if the first write recovery signal and the second write recovery signals φ _WR1 and φ _WR2 were set to the "L" level, respectively, but since they become "L" level with a slight delay, the timing t V _2L ′ to V _2L ″ by the current supply means 9 ″ by ₅ ,
Set V _2H ′ to V _2H ″.

From the time when timing t ₅ is reached, the clamping means 9
begins to operate substantially. That is, the clamping means 9 inverts the signal of WE'.
This is because the current driving capability is lower than that of the current supply means 9'', although it is already operating when the WE' signal reaches the "H" level and the CSA2 signal reaches the "H" level.

By this clamping means 9, the common data line
V _2H ″ and V _2L ″ of CD ₀ and CD ₁ are brought to states V _2H and V _2H that are closer to V _2H and V _2L .

That is, the clamping means 9 is connected to the common data line.
The levels of CD ₀ and CD ₁ are set to the second potential states V _2H and V _2L
It works to bias around the intermediate level of V ₀ and clamp it to that level.

Therefore, if the first and second write recovery signals φ _WR1 and φ _WR2 have a level difference in the second potential state,
Even if it becomes "L" level before 0.3V is obtained, that level is guaranteed by the clamping means 9,
It can even go down to 0.3V.

Memory cell MS _no is selected by switching address signal Ai at timing _t6 .

The memory cell MS _no has a potential V _2H determined by the load means Q ₇ ′, MISFETQ ₁ ′, Q ₃ ′ at its cross-connection point A′.
However, the load means Q ₃ ′, MISFETQ ₂ ′,
The potential V _2L determined by Q ₄ ' is stored and held.

Therefore, the state is completely opposite to that of the common data lines CD ₀ and CD ₁ .

The V _2H and V _2L of the common data lines CD ₀ and CD ₁ are set to V _2H and V _2L in the memory cell MS _no , and are inverted to V _2L and V _2H .

Incidentally, since the above-mentioned V _2H and V _2L are almost equal to V _2H and V _2L , the level correction in the memory cell MS _no is faster than that in the MIS memory circuit shown in FIG.

At timing t ₇ , the common data lines CD ₀ ,
Since V _2L and V _2H are obtained as the read data of the memory cell MS _no in CD ₁ , it is amplified by the read circuit 7' and the “L” level D _OUT is output as the read data from the input/output terminal I/O. Output.

In addition, in the readout circuit of the present invention, when the bias source V _CC is set to 4.5V, for example, 2.5V and 2.8V are obtained as V _2L and V _2H , respectively, so a TTL logic level output from the readout circuit can be easily obtained. It will be done.

The operation of the MIS memory circuit using the data line potential setting circuit 9 according to the present invention has been described above, and the object of the present invention can be achieved for the following reasons.

1. Switching means 9' is connected between the common data lines, and the charge of the capacitance of one common data line is discharged to the capacitance of the other common data line via the switching means 9'. By lowering and raising the line level, the difference in level between the two is brought closer. (According to the conventional circuit, the levels of both common data lines are brought close to each other by only raising the level of the other common data line.) Furthermore, the switching means 9' outputs the first write recovery signal. Since a potential of 2·V _cc −V _th is applied to its gate by φ _WR1 , it operates in a non-saturated state, and its operating resistance is also small, so the rise and fall mentioned above are steep. There is. Furthermore, since charge is supplied to the capacitance of the other common data line by the current supply means 9'', the rise of the level of the other common data line becomes faster together with that of the switching means 9', and as a result, both common data lines The levels between the data lines will approach that much faster.

From the above, the level difference in the second potential state can be obtained faster than the conventional data line potential setting circuit.

2. A switching means 9' is connected between the common data lines, and the charge of the capacitance of one common data line is discharged to the capacitance of the other common data line via the switching means 9', and the switching means 9' Because it operates in a non-saturated state, the falling characteristics of one common data line and the rising characteristics of the other common data line can be made almost the same, and as a result, the level difference in the second potential state is almost the same. obtained near the second potential state.

Therefore, the time required to bring the memory cell into the second potential state can be shortened.

3 The switching means 9' and the current supply means 9'' output the first and second write recovery signals φ when the level between the common data lines approaches the second potential state.
Since _WR1 and _φWR2 are at the "L" level, they are not operating, and the level of the common data line does not rise to a level higher than the second potential state.

4 After the switching means 9' and the current supply means 9'' raise the level of the common data line above the second potential state and stop the operation, the switching means 9' and the current supply means 9'' raise the level to the second potential state.
Since the clamping means 9 is provided to lower the potential level to around the potential state of the memory cell, there is no need to lower the level of the memory cell itself, and as a result, the second potential state is obtained quickly.

As another embodiment of the present invention, data line potential setting circuits shown in FIGS. 8 to 10 can be considered.

In the embodiment shown in FIGS. 8a to 8f, a data line potential setting circuit is constructed using only switching means 9' and current supply means 9''.

The data line potential setting circuit of FIG. 8a is obtained by removing the clamping means 9 from the data line potential setting circuit 9 of FIG. The second potential state can be obtained more quickly than the conventional data line potential setting circuit shown in FIG.

The data line potential setting circuit of FIG. 8b sets the value of the bias source connected to the current supply means so that the level of V _2H in the second potential state is the level of V _2L , or the threshold voltage of the MISFET. (approx. 0.7V)
It is approximately equal to the sum of Note that MISFETQ ₉ and Q ₁₀ are enhancement types.
Assuming that it is a MISFET and is operating in the saturation region, the level of the common data line will not rise above the second potential state. Therefore, it is not necessary to use the clamping means 9 in this case.

The data line potential setting circuit shown in FIG. 8c is configured to apply the first write recovery signal φ _WR1 to the switch means 9' and the current supply means 9, and MISFETQ ₉ , Q of the current supply means 9''. By operating the common data line ₁₀ in a non-saturated state, charging of one common data line is rapidly performed together with the switching means 9'.

The data _line potential setting circuit shown in FIG. 8d is similar to the data line potential setting circuit shown _{in FIG .}
The level of the common data line is set to be approximately equal to the level of _V2L , or a level in between, and the level of the common data line is prevented from rising above the level of the second potential state.In this circuit, Neither the clamping means 9 nor the clamping means 9 need be used.

The data line potential setting circuit in FIG. 8e is a current means 9.
The bias source is the first or second write recovery signal φ _WR1 , φ _WR2 , and in this case as well, the same effects as in FIGS. 8 a to 8 d can be obtained.

The data line potential setting circuit shown in FIG. 8f is such that the current means 9'' is always operated.
In this case as well, the second potential state can be obtained faster than in the conventional data line potential setting circuit due to the action of the switching means 9'. However, in the case of this circuit, the driving ability of the current supply means needs to be smaller than that of the circuit means (for example, the write circuit 6) that brings the data line to the first potential state.

The bias sources V _cc ′ and V _cc ″ used in _the data line potential setting circuits shown _in FIGS. You can get it.

The data line potential setting circuit shown in FIG. 9 is another embodiment in which the switching means 9', the current supply means 9'', and the clamp means 9'' are arranged. The circuit shown in FIG. 8c is used, and it is possible to obtain substantially the same effect as the data line potential setting circuit shown in FIG. Of course, it is also conceivable to add a clamp means to the circuit e to configure a data line potential setting circuit.

The data line potential setting circuit shown in FIG. 10 is constructed of only switching means 9' and clamping means 9''. In this case, during the period T ₂ ' shown in FIG. 9'' can prevent the potential level of the data line from rising undesirably.

Note that although MISFET is used as the switching means 9', a bipolar transistor may also be used. Further, the number of elements formed between the common data lines is not limited to one, but may include a plurality of logic circuits.

The current supply means 9'' is composed of an enhancement type MISFET, but a depletion type may also be used.Furthermore, it may be a current supply means such as a bipolar transistor, a diode, a resistor, etc. other than the MISFET. It may include a plurality of elements connected between the bias source and the data line.

Further, the clamping means 9 is not limited to the one shown in FIG. 5, and various modified circuits having the same function can be considered.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram using the data line potential setting circuit.
MIS memory circuit diagram, Figure 2 is a write circuit diagram used in the MIS memory circuit, Figure 3 is a read circuit diagram used in the MIS memory circuit, Figure 4 is the timing of the MIS memory circuit in Figure 1. Chart diagram, FIG. 5 is a schematic MIS memory circuit diagram using the data line potential setting circuit according to the present invention, FIG. 6 is a write recovery signal generation circuit diagram, and FIG. 7 is a diagram of the write recovery signal generation circuit.
Timing chart diagrams of the MIS memory circuit, FIGS. 8a, b, c, d, e, f, FIGS. 9 and 10 are data line potential setting circuit diagrams according to other embodiments of the present invention, and FIG. 11 is the voltage conversion circuit diagram, the 12th is
MISFET output voltage (V _DS ) - output current (I _DS )
FIG. 3 is a characteristic diagram showing characteristics. 1...Memory matrix, 2...Row selection address decoder, 3...Column gate means, 4...
Column selection address coder, 5... Load means, 6...
Write circuit, 7', 7... Read circuit, 8...
...Conventional data line potential setting circuit, 9...Data line potential setting circuit according to the present invention, 10...Write recovery signal generation circuit, 11... Potential conversion circuit.

Claims (1)

[Claims] 1. A bias circuit that receives a power supply voltage of the circuit and forms a bias voltage smaller than the applied power supply voltage, and between a pair of data lines to which complementary data signals are to be applied and the output of the bias circuit. is set to an operating state when the potential state of the pair of data lines is transferred from one state to another state, and in the operating state, the potential of the pair of data lines is set to be the same as the high level and low level of the complementary data signal. 1. A data line potential setting circuit comprising: switching means for forcing an intermediate level. 2 The switching means includes a first switching MISFET provided between the output of the bias circuit and the pair of data lines, and a second switching MISFET provided between the pair of data lines.
Claim 1 consisting of
The data line potential setting circuit described in . 3. Current supply means for supplying current from a power supply terminal to a pair of data lines to which complementary data signals are applied, and switching means for causing current to flow from the pair of data lines to a grounding point of the circuit, By operating the means, the potential of the pair of data lines before the complementary data signal is applied is at a level intermediate between the high level and the low level of the complementary data signal, and the current supply means and the switching means are connected to each other. A data line potential setting circuit configured to force a level brought about by co-operation. 4. The current supply means includes a first switching element provided between the pair of data lines, and a plurality of second switching elements provided between each of the data lines and the power supply terminal. A data line potential setting circuit according to claim 3, characterized in that: 5. The data line potential setting circuit according to claim 4, wherein the first and second switching elements and the switching means are MISFETs. 6. A differential amplifier having a memory matrix, a column gate means, a pair of common data lines coupled to the memory matrix via the column gate means, and an input terminal coupled to the pair of common data lines. and a potential setting circuit, wherein the potential setting circuit includes a bias circuit that receives the power supply voltage of the circuit and forms a bias voltage lower than the power supply voltage of the circuit to which it is applied, and an output of the bias circuit and the potential setting circuit. When the potential state of the pair of common data lines is transferred from one state to another state, the potential state of the pair of common data lines is set to the operating state, and in the operating state, the potential of the pair of common data lines is set to the above level. 1. A MIS memory circuit comprising switching means for forcing a complementary data signal applied to the pair of common data lines to an intermediate level between a high level and a low level using an output voltage of a bias circuit. 7 The switching means operates together with a pair of first switching MISFETs provided between the output of the bias circuit and the pair of common data lines, and the first switching MISFET provided between the pair of common data lines. 7. The MIS memory circuit according to claim 6, comprising a second switching MISFET. 8. A differential amplifier having a memory matrix, a column gate means, a pair of common data lines coupled to the memory matrix via the column gate means, and an input terminal coupled to the pair of common data lines. and a potential setting circuit, the potential setting circuit includes a current supply means for supplying current from a power supply terminal to the pair of common data lines, and a current supply means for supplying current from the pair of common data lines to a grounding point of the circuit. and switching means for causing the potential of the pair of common data lines to flow to a level intermediate between the high level and the low level of the complementary data signal applied to the pair of common data lines by the operation of the switching means. An MIS memory circuit configured to force the current to a level brought about by cooperation between the current supply means and the switching means. 9 The above current supply means and switching means are
Claim 8 consisting of MISFET
MIS memory circuit. 10 The current supply means is provided in series between the power supply terminal and the pair of common data lines, and includes a switching MISFET that is controlled to have an operation period that overlaps with at least the operation of the switching means. The MIS memory circuit according to claim 9, characterized in that: 11. One of claims 8 to 10, characterized in that the memory matrix is composed of a plurality of static type memory cells.
MIS memory circuit described in.