JPS6255727B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a transversal equalizer that has both an automatic equalization function and a fixed equalization function. In high speed data transmission, some equalization is required to eliminate intersymbol interference caused by telephone lines. For example, the International Telegraph and Telephone Advisory Committee
We are looking at adding an automatic equalizer to the 4800bps modem and a fixed equalizer to the 2400bps modem. The automatic equalizer performs equalization using a transversal filter with adjustable tap coefficients, and the principle of operation will be briefly explained with reference to FIG. In Fig. 1, 1 ₁ to 1 _N are tapped delay lines, 2
₁ to 2 _N are integrator groups, 3 ₁ to 3 _N and 4 are each tap output xi-j (unequalized signal) of the tapped delay lines 1 ₁ to 1 _N , and each of the integrator groups 2 ₁ to 2 _N. A first multiplier group and an adder perform a convolution operation with the output Cj (tap coefficient), and the output of the adder 4 becomes the equalized output signal yi. 5 ₁ ~ 5 _N is a delay line with tap 1 ₁
~1 _N tap outputs xi-j and the error signal ei (the difference between the equalized signal yi and the reference signal ai) are correlated with each other.
multiplier groups 6 ₁ to 6 _N are second multiplier groups 5 ₁ to 6
5 _N is a sensitivity controller group that multiplies each output by a sensitivity constant α, and by inputting each output of this sensitivity controller group 6 ₁ to 6 _N to each of the integrator groups 2 ₁ to 2 _N , Each tap coefficient is controlled so that the error signal is minimized. Therefore, ν of the jth tap
The tap correction for the second time can be expressed as follows, where the number of taps is N. Cj ⁽ 〓 ⁾ ＝Cj ⁽ 〓 ^-1) −α・ei・xi−j …(1) However, ei＝yi−ai,

[Formula] Delay line with taps 1 ₁ to 1 _N , first multiplier group 3
₁ to 3 _N and the adder 4 constitute a transversal filter. Therefore, the error signal ei is set to zero,
If an appropriate fixed tap coefficient is given by RM or the like, this automatic equalizer operates as a fixed equalizer. For example, store 7 sets of impulse responses with inverse characteristics of each link of transport 1, 2, ..., 7 links as tap coefficients in a coefficient memory such as RM, select any one set of them, By performing a convolution operation with the equalized input signal, an equalized output signal can be obtained. Now, when realizing an automatic equalizer with the principle configuration as shown in Fig. 1, in order to minimize the circuit scale, arithmetic units such as multipliers or adders are used in time-division multiplexing, and the input signal xi is stored. A configuration is adopted in which data registers for storing tap coefficients Cj and tap registers for storing tap coefficients Cj are provided for the number of taps (N words). The number of multipliers and adders required here is determined from the relationship between the input signal speed and the calculation processing speed.
In the case of automatic equalization, the unequalizer input signal xi and tap coefficient Cj are shifted in registers,
An equalized output signal is obtained by successively adding these products, but in the case of fixed equalization, there is no need to use a tap register if the tap coefficients are given directly from the coefficient memory. Furthermore, in the correction formula for the tap coefficient shown in equation (1), the sensitivity constant α generally takes a value sufficiently smaller than 1. Therefore, the bit length per word of the tap register that stores the tap coefficients that are successively modified by equation (1) must be longer than that of the data register. From the above circumstances, it can be seen that in the case of fixed equalization, the capacity of the coefficient memory can be reduced by using the tap register as a part of the data register. For example, if the tap register is made double precision than the data register, if the tap register is used as the data register, seven types of equalization characteristics can be obtained by storing three types of tap coefficient series in the coefficient memory. The present invention has been made with attention to these points, and its purpose is to share the transversal filter section and, especially in fixed equalization, by also using the tap register used during automatic equalization as a data register. An object of the present invention is to provide a transversal equalizer that can selectively obtain an automatic equalization function and a fixed equalization function with a minimum circuit configuration. Hereinafter, the present invention will be explained in detail with reference to Examples.
FIG. 2 shows an embodiment of the present invention, where the number of taps is N, multiplication and addition for N convolution operations, multiplication for N interphase operations, and subtraction for tap correction. This is an example of a configuration in which the following are performed by using arithmetic sections each consisting of one serial/parallel multiplier and one accumulator in a time-sharing manner. This is a time-division multiplexing degree that is fully achievable when creating a single-chip equalizer for a modem with a data rate of 4800 bps or less using current semiconductor manufacturing technology. In FIG. 2, 7 is a data register, 8 is a first tap register, and 9 is a second tap register, each of which has N words, and n words per word.
Suppose it has the size of a bit. 10 is serial/
11 is a parallel input/parallel output type shift register of n bits or less; 12 is an accumulator;
is adder 12 ₁ and 2n bit shift register 1
It is composed of 2 and ₂ . 13 is a scaler, 14 is
A coefficient memory consisting of a ROM, 15 an n-bit buffer, and 16 to 23 a group of selectors for time division calculations. The operations of the selector groups 16 to 23 are as follows. The selector 16 selects the unequalized input signal sequence xi input from the terminal 24 or the output of the data register 7, and inputs the selected signal to the data register 7. The selector 17 selects the output of the adder ₁₂₁ , the output of the buffer 15, or the output of the first tap register 8, and inputs the selected output to the first tap register 8. The selector 18 selects the output of the adder ₁₂₁ , the output of the buffer 15, or the output of the second tap register 9, and inputs the selected output to the second tap register 9. The selector 19 selects the output of the data register 7, the output of the first tap register 8, or the output of the second tap register 9, and inputs it to the serial input terminal of the multiplier 10. The selector 20 selects the error signal series ei input from the output of the second tap register 9 or the terminal 25, and inputs it to the serial input terminal of the parallel input/parallel output shift register 11. The selector 21 selects the output of the multiplier 10 or the output α, ei, and xi-j of the scaler 13 and inputs it to one input terminal of the _{adder 121} .
The selector 22 is the output of the first tap register 8.
C′j, the output C″j of the second tap register 9 or the output of the accumulator 12, and the adder 1
2 Input to the other input terminal of ₁ . Finally, the selector 23 selects the output of the accumulator 12 or the unequalized input signal xi and inputs it to the buffer 15. The output of this buffer 15 is output from a terminal 26 and becomes an equalized output signal yi. First, the operation of this embodiment as an automatic equalizer will be explained. Unequalized input signal xi, equalized output signal yi and error signal ei are 1 word n bits, tap coefficient Cj
is one word of 2n bits, and the lower n bits (C'j) and upper n bits (C''j) of the tap coefficient Cj are divided and stored in the first tap register 8 and the second tap register 9, respectively. That is, the tap register as a whole has twice the precision of the data register 7.The parallel input terminal of the multiplier 10 has a second
The output C″j of the upper n bits of the tap register 9 is serial/parallel converted by the shift register 11 and inputted.The output of this multiplier 10 is
The output of the adder ₁₂₁ is also 2n bits, and the lower n bits of the output of the adder ₁₂₁ are input to the first tap register 8 and the upper n bits are input to the second tap register 9, respectively. Now, one baud rate or one sampling rate T is divided into 3N sub-intervals t. The length of one subinterval t is 2nτ, where τ is the clock rate. 1/ at the beginning of time T
3, that is, the convolution operation is performed in the period T1 of Ot ~ (N-1)t, and the remaining 2/3, that is, Nt ~ (2N-
1) Correlation calculation and tap correction are performed in a period T2 of t and a period T3 of 2Nt to (3N-1)t. The unequalized input signal xi and the error signal ei are input to the equalizer once during time T. The input signal xi is, for example, a demodulated unequalized signal of an amplitude modulation signal, and the error signal ei is the output signal yi minus its discrimination output or reference signal ai. Period T1
, the unequalized input signal xi (n bits) is selected by the selector 16 and input to the data register 7, sequentially shifted within the data register 7, selected by the selector 19, and input to the serial input signal of the multiplier 10. Become. Similarly, the tap coefficient C''j (n bits) is sequentially shifted in the second tap register 9, and then transferred to the selector 20 and the shift register 11.
becomes the parallel input signal of the multiplier 10. Here, each register 7 by the lines 27, 28, 29,
The feedback of outputs 8 and 9 is for correlation calculation and tap correction in periods T2 and T3. The multiplier 10 successively outputs N products C″j·xi−j (2n bits), and the selector 21,
Adder 12 ₁ , shift register 12 ₂ , line 30
and are sequentially added by the selector 22. i.e. The following calculations are performed, and yi' is further shortened to n bits by rounding or truncation, and then passes through the selector 23 and buffer 15 to become the equalized output signal yi. Next, in periods T2 and T3, one tap correction is performed in a time of 2t, that is, 4nτ. That is, in the first half t, a correlation calculation is performed between the unequalized input signal xi and the error signal ei, and in the second half t, tap correction is performed. The serial input signal of the multiplier 10 is the output of the data register 7 as in the period T1, and the parallel input signal is the error signal ei (n bits) converted into parallel. Output ei・xi of multiplier 10
The value α·ei·xi−j (2n bits) obtained by multiplying -j by the sensitivity constant α by the scaler 13 is inputted to one input terminal of the adder ₁₂₁ via the line 30 and selector 21. The other input terminal of the adder ₁₂₁ is connected to n-bit first and second tap registers 8 and 9 via lines 32 and 33 and a selector 22, respectively.
The outputs C′j and C″j of Then, it is input to the first and second tap registers 8 and 9. That is, the νth correction of the jth tap coefficient is Cj ⁽ 〓 ⁾ = Cj ⁽ 〓 ^-1) −α・ei・xi−j …( 3), and this is performed sequentially for N taps.Next, the operation as a fixed equalizer will be explained.The operation as a fixed equalizer is basically the automatic equalization described above. The only operation is the same as the convolution operation in the period T1 in the
It is repeated in 3. In this case, multiplier 1
A parallel input signal of 0 becomes the output of the coefficient memory 14. Here, the coefficient memory 14 stores, for example, transport 0,
Among the 1, 2, . . . 7 links, the impulse responses l1j, l2j, l3j with inverse characteristics of the 1st, 2nd, and 4th links are stored as fixed tap coefficients. 0,
The desired equalized output signals of the 1, 2, . . . 7 links are, for example, the 3-bit control code L
1, L2, and L3.

[Table] That is, first, the unequalized input signal xi is input to the data register 7, and is also input to the buffer 15 via the line 35 and the selector 23. Period T
1, the output xi-j of the data register 7 is selected by the selector 19, and the impulse response of the opposite characteristic of 1 link from the coefficient memory 14 is selected by the selector 19.
A convolution operation with l1j is performed. The calculation effect is input to the buffer 15 if L1="1". If L1="0", the contents of buffer 15 are
xi remains. During period T2, the output of the buffer 15 passes through the line 36 and the selector 17 to the first
It is input to the tap register 8 of. The output j1i of the first tap register 8 when L1="1" is selected by the selector 19, and this and the impulse response of the two links from the coefficient memory 14 have opposite characteristics.
A convolution operation with l2j is performed. The result of the calculation Similarly, if L2="1", it is input to the buffer 15. During the period T3, the output of the buffer 15 is input to the second tap register 9 via the line 36 and the selector 18. The output g2i of the second tap register 9 when L2="1" is selected by the selector 19, and a convolution operation is performed between this and the impulse response l3j of the 4-link inverse characteristic from the coefficient memory 14. The result of the calculation Similarly, if L3="1", it is input to the buffer 15. In this way, the equalized output signal yi becomes a signal subjected to arbitrary link equalization by the combination of control codes L1, L2, and L3. That is, when the combination of L1, L2, and L3 is A, the unequalized input signal xi, which corresponds to a signal subjected to O-link link equalization, is output as is as the equalized output signal yi, and when the combination is B, xi The link-equalized signal for 1 link, which is the convolution result of If the link-equalized signal is D, then the 3-link link equalization is performed, which is the result of convolution of the 1-link link-equalized signal and the 2-link impulse response with the opposite characteristic. If the signal is E, it is a signal that has been subjected to link equalization of 4 links, which is the result of the convolution operation of xi and the impulse response with the inverse characteristics of 4 links.If the signal is F, it is a signal that has been subjected to link equalization of 1 link. If the signal subjected to link equalization of 5 links, which is the result of the convolution calculation between If the signal subjected to link equalization of 6 links, which is the result of convolution with the response, is H, it is the result of convolution of the signal subjected to link equalization of 3 links and the impulse response of 4 links with the opposite characteristics. Signals subjected to link equalization for 7 links are respectively output. In addition, in the case of B, C, and E, xi is the first
The impulse responses of the inverse characteristics of the links 1, 2, and 4 are given as the output of the data register 7, which is a storage means, and are stored in the coefficient memory 1, which is a third storage means.
4 as a fixed tap coefficient. Also,
A signal with link equalization of 1 link used in the case of D and F, a signal with link equalization of 2 links used in the case of G, and a link equalization of 3 links used in the case of H. The signal subjected to
Both are given as outputs of tap registers 8 and 9, which are second storage means. Conventionally, the initial value of the tap coefficient in automatic equalization is generally set to 1.0 for the center tap and 0 for the other taps, but according to the present invention, the coefficient memory 1
Using the tap coefficients for fixed equalization stored in the tap coefficients 4, any one set of them is converted from parallel to serial in the shift register 11, and the tap coefficients for automatic equalization are sent to the tap registers 8 and 9 via the line 37. It is also possible to set it as the initial value of the tap coefficient. By doing so, it is possible to increase the convergence speed of the tap coefficients. As explained above, according to the present invention, in the case of automatic equalization and the case of fixed equalization, the transversal filter section (in the example of FIG. The minimum circuit configuration is basically just adding a third storage means (coefficient memory 14 in the example of Fig. 2) that provides fixed equalization tap coefficients to the automatic equalizer. Accordingly, it is possible to provide a transversal equalizer having both automatic equalization and fixed equalization functions. Furthermore, in the present invention, especially during fixed equalization,
The unequaled output of the first storage means (data register 7) is stored in a second storage means (tap registers 8 and 9 in the example of FIG. 2) for storing adjustable tap coefficients in automatic equalization. The convolution result of the input signal and the tap coefficient which is the output of the third storage means (coefficient memory 14), or the convolution result of the convolution calculation result and the output of the third storage means is accumulated, and the first a convolution calculation result of the output of the storage means and the output of the third storage means;
Alternatively, by selectively extracting the convolution result of the output of the second storage means and the output of the third storage means as an equalized output signal, the type of tap coefficients stored in the third storage means can be Since a large number of equalization characteristics can be obtained, there is an advantage that the capacity of the third storage means can be significantly reduced. Next, another embodiment of the present invention will be described with reference to FIGS. 3 and 4. The embodiment of FIG.
In addition to the impulse responses lij, l2j, l3j with the opposite characteristics of the transport links 1, 2, and 4, tap coefficients l0j of the center tap 1.0 and other taps 0.0 are stored, and the above-mentioned control codes L1, L2, L3 are stored. When all are "0", this tap coefficient l0j is selected. Further, in this embodiment, the tap coefficients Cj are successively stored in the first and second tap registers 8 and 9 during automatic equalization. Along with this, the output of the second tap register 9 fed back via the line 38 is newly added to the input of the selector 17, increasing the number of inputs to the selector 17, and one input of the selector 18 is connected to the output of the adder ₁₂₁ . 1
3. Except for the fact that the output of the first tap register 8 is changed to the output of the tap register 8, that the output of the first tap register 8 is removed from the three inputs of the selector 22, and that the selector 22 has two inputs, and that a buffer is not required. The operation is basically the same as in FIG. In each of the above embodiments, fixed equalization for the carrier link, ie, delay characteristics, of the telephone line has been described, but fixed equalization for attenuation compensation, ie, amplitude characteristics, of the subscriber line can also be performed using similar means. Furthermore, the number of convolution operations performed between one baud rate or one sampling rate T in fixed equalization is not limited to three. Furthermore, the present invention can be easily extended to equalizers for general complex signals, such as phase modulated signals. FIG. 4 shows an embodiment for such a complex signal, which is composed of two equalizers, an in-phase part and a quadrature part. In the figure, circuits with the same symbols as in FIG. 2 have the same functions, and the subscript p indicates the in-phase part, and the subscript q indicates the orthogonal part. In the figure, the selectors for the fed-back input signals of the data registers _7p , _7q , the first tap registers _8p , _8q and the second tap registers _9p , _9q are omitted. The operation of this embodiment is basically the same as that of the previous embodiment, but is more complicated because it handles complex signals. The selectors 19 _p and 19 _q have six inputs, namely the outputs of the in-phase and quadrature section data registers 7 _p and 7 _q , the outputs of the first in-phase and quadrature section tap registers 8 _p and 8 _{q, and the outputs of the second in-phase and quadrature section data registers 7 p and 7 q} , respectively. The outputs of the orthogonal section tap registers 9 _p and 9 _q are selected and inputted to the serial input terminals of the in-phase section and quadrature section multipliers 10 _p and 10 _q , respectively. The selector 20 _p selects the in-phase component e _p of the error signal and the output of the tap register 9 _p , and inputs them to the parallel input terminal of the in-phase multiplier 10 _p .
The same applies to the selector _20q . The outputs of the in-phase multiplier 10 _p in the convolution operation are Cpi xpi-j and Cpj xqi-j in the case of automatic equalization, and lpj xpi-j and lpj xqi-j in the case of fixed equalization. .
Here, xpi-j and xqi-j are the outputs of the data registers 7 _p and 7 _q , respectively, Cpj and Cqj are the outputs of the tap registers 9 _p and 9 _q , respectively, and lpj and lqj are the in-phase part and quadrature part coefficient memories 14 _p , respectively. This is the output of 14 _q . The outputs of the orthogonal multiplier _10q are Cqi.xpi-j and Cqj.xqi-j in the case of automatic equalization, and lqj.xpi-j and lqj.xqi-j in the case of fixed equalization.
The output of the in-phase part multiplier 10 _p in the correlation calculation is e _{p
j xpi-j} and e _pj

Claims (1)

[Scope of Claims] 1. A first storage means for storing unequalized input signals, a second storage means for storing tap coefficients used when operating as an automatic equalizer, and a fixed tap coefficient. a third storage means that stores in advance, a calculation means that selects the output of any two of the first to third storage means and performs a convolution operation, and when operating as an automatic equalizer, The tap coefficients are stored in the second storage means in the direction where the difference between the reference signal and the convolution result of the output of the first storage means obtained by the calculation means and the output of the second storage means is minimized. means for sequentially correcting; and selectively modifying the convolution result of the output of the first storage means and the output of the third storage means or the result of the convolution operation of the output of the second storage means and the third storage means. means for transferring and accumulating the second storage means, and when operating as an automatic equalizer, extracting the convolution result of the output of the first storage means and the output of the second storage means as an equalized output signal; When operating as a fixed equalizer, the unequalized input signal, or the convolution result of the output of the first storage means and the output of the third storage means, or the output of the second storage means and the third 1. A transversal equalizer comprising means for selectively extracting the result of convolution with the output of the storage means as an equalized output signal. 2. The second storage means is characterized in that when the transversal equalizer operates as an automatic equalizer, part of the tap coefficients stored in the third storage means is given as an initial value. A transversal equalizer according to claim 1.