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JPS6254457A - Input/output circuit for integrated circuit - Google Patents

Input/output circuit for integrated circuit

Info

Publication number
JPS6254457A
JPS6254457A JP19427885A JP19427885A JPS6254457A JP S6254457 A JPS6254457 A JP S6254457A JP 19427885 A JP19427885 A JP 19427885A JP 19427885 A JP19427885 A JP 19427885A JP S6254457 A JPS6254457 A JP S6254457A
Authority
JP
Japan
Prior art keywords
circuit
signal
pin
input
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19427885A
Other languages
Japanese (ja)
Inventor
Osamu Shimano
嶋野 收
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19427885A priority Critical patent/JPS6254457A/en
Publication of JPS6254457A publication Critical patent/JPS6254457A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To realize a multi-functional high integration by a method wherein AC signals inputted at an IC first pin is supplied to a signal-processing circuit through a buffer circuit capable of transmitting only AC signals and, simultaneously, DC signals are caused to be inputted into or outputted from a DC signal circuit in the IC at said IC first pin. CONSTITUTION:DC signals 26 are outputted at a pin 23 and, simultaneously, AC signals 21 may be supplied to a chroma signal processing circuit 25 through the pin 23 and buffer circuit 24 because changes in the DC potential at the pin 23 are stopped by the buffer circuit 24. That is to say, the buffer circuit 24 provided between the pin 23 and chroma signal processing circuit 25 enables a single pin to serve multiple purposes. In a circuit designed as such, the inputting of AC signals, inputting of DC signals, and outputting of DC signals may be accomplished by using a single pin. The number of pins required in an IC may be decreased and a circuit, capable of a multiplicity of functions and enhanced in integration, may be built in a single chip.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は交流信号及び直流信号の入出力用ビン数を減ら
すことを可能とした集積回路の入出力回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an input/output circuit for an integrated circuit that makes it possible to reduce the number of input/output bins for AC signals and DC signals.

〔発明の技術的背景〕[Technical background of the invention]

近年、電子機器に使用されるIC(集積回路)では、よ
り多くの回路機能を1つのチップ上に構成する多機能高
集積化が進展しつつある。現在。
2. Description of the Related Art In recent years, ICs (integrated circuits) used in electronic devices are becoming increasingly integrated with multiple functions, in which more circuit functions are configured on one chip. the current.

テレビジ曽ン受y機に使用さ九るICは、所謂1チップ
ICも出現し、ICの使用ビン数は厳犬64に及んでい
る。
Among the ICs used in TV receivers, so-called 1-chip ICs have also appeared, and the number of ICs used has reached 64.

第3図は従来のテレビジョン受像機ビデオ・クロマ回路
用ICに使用される代表的な入出力回路の一例を示して
いる。交流信号1はコンテンツCIを介してIC20入
力用ビン3に加えられ、このピン3よりIC内のクロマ
信号処理回路4へ供給される。クロマ信号処理回路4は
トランジスタQl〜Q6を用いた2重平衡調調回路で構
成されている。一方、IC2には直流(4号の出力用ビ
ン5及び直流信号の入力用ピン6が設けられている。出
力用ピン5については、IO2内に(4成さ扛た50/
60Hz判別回路7よりフィールド周波数(50I(z
若しくは60Hz)の判定信号(直流信号)8を得、こ
れをトランジスタQ7を用いた増幅器9を通して出力用
ピン5に導き、更にIC外部の増幅器10を経てフィー
ルド周波数切換用信号として外部回路へ出力される。入
力用ピン6については、ミュート信号(直流信号)11
が増幅器12を通して入力用ビン6に加えられ、このピ
ン6よりトランジスタQ8.Q9を用いた差動増幅器1
3及びトランジスタQloを用いた増幅器14を経てミ
ュート回路15へ供給される。ミュート回路15は外部
入力されるミュートff4号によってビデオ信号を一挙
に減衰すべく構成された回路である。
FIG. 3 shows an example of a typical input/output circuit used in a conventional video chroma circuit IC for a television receiver. The AC signal 1 is applied to the input bin 3 of the IC 20 via the content CI, and is supplied from this pin 3 to the chroma signal processing circuit 4 in the IC. The chroma signal processing circuit 4 is composed of a double balanced adjustment circuit using transistors Ql to Q6. On the other hand, the IC2 is provided with a DC signal output pin 5 and a DC signal input pin 6.
The field frequency (50I(z
A judgment signal (DC signal) 8 of 60 Hz) is obtained, which is led to the output pin 5 through an amplifier 9 using a transistor Q7, and further outputted to an external circuit as a field frequency switching signal via an amplifier 10 outside the IC. Ru. For input pin 6, mute signal (DC signal) 11
are applied to input pin 6 through amplifier 12, and from this pin 6 transistors Q8. Differential amplifier 1 using Q9
3 and an amplifier 14 using a transistor Qlo, the signal is supplied to a mute circuit 15. The mute circuit 15 is a circuit configured to attenuate the video signal all at once using externally inputted mute FF4.

〔背九技術の間2重点〕 ところで、IC特にアナログICでは、その外囲器との
関係からピン数を増大さぜろのに限度がある。従って、
より多機能高集積化を実現するためには−ビンの有効利
用技術が必要となる。
[Second point in technology] By the way, in ICs, especially analog ICs, there is a limit to how much the number of pins can be increased due to the relationship with the package. Therefore,
In order to achieve more multi-functionality and higher integration, technology for effective use of bins is required.

ところが、上記従来のICでは、交流信号の入力用ビン
3と直流信号の入力用ピン6又は出力用ビン5は、回路
構成上1号に必要とされ、このためビン数を絨少させろ
ことは回路的に不可能であるという欠点があった。
However, in the above-mentioned conventional IC, the input bin 3 for AC signals and the input pin 6 or output bin 5 for DC signals are required in No. 1 due to the circuit configuration, so it is difficult to minimize the number of bins. The drawback was that it was impossible due to the circuit.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、1つのピンで交流信号の入力と直流信
号の入力又は出力を行うことができ、多機能高集積化に
適した集積回路の入出力回路を提供することにある。
An object of the present invention is to provide an input/output circuit for an integrated circuit that is capable of inputting an AC signal and inputting or outputting a DC signal using one pin, and is suitable for multifunctional and highly integrated circuits.

〔発明の概要〕[Summary of the invention]

本発明の回路は、IC内部に交流信号用及び直流信号用
の機能別回路が構成され、交流信号及び直流信号がピン
入力又はピン出力されるICにおいて、ICの第1ビン
より入力される交流信号を。
The circuit of the present invention is an IC in which functional circuits for AC signals and DC signals are configured inside the IC, and AC signals and DC signals are input or output via pins. Signal.

交流信号のみ伝送するバッファ回路を通して信号処理回
路へ供給するように構成し、同時にIC内部の直流信号
回路に対しては上記第1ピンより直流信号を入力又は出
力するように構成したものである。
The AC signal is configured to be supplied to the signal processing circuit through a buffer circuit that transmits only the AC signal, and at the same time, the DC signal is input to or output from the first pin to the DC signal circuit inside the IC.

〔発明の実施例〕[Embodiments of the invention]

以下、図面に基づいて本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail based on the drawings.

第1図は本発明の集積回路の入出力回路の一実施例を示
す回路図である。この実施例は、第3図の交流信号入力
回路(クロマ信号入力回路)と直流信号出力回路(50
/60Hz判別信号出力回路)の2つの入出力回路を1
つのビン使用で実現した回路例を示している。
FIG. 1 is a circuit diagram showing one embodiment of an input/output circuit of an integrated circuit according to the present invention. This embodiment consists of an AC signal input circuit (chroma signal input circuit) and a DC signal output circuit (50
/60Hz discrimination signal output circuit).
An example of a circuit realized using two bins is shown.

この図において、交流信号21けコンデンサC1lを介
してIC22のピン23に加えられ、このピン23を通
じ、バッファ回路24を介してクロマ信号処理回路25
へ供給される。バッフ1回路24はトランジスタQll
とそのエミッターアース間に接続された定′眠流源Il
lとからなり、交流信号21はピン23よりトランジス
タQ1tのベースに入力されトランジスタQllのエミ
ッタよりコンデンサC12を通して次段のクロマ信号処
理回路25へ供給される。この場合、バッフ1回路24
は直流分を遮断し交流信号のみをクロマ信号処理回路2
5へ伝達する。クロマ信号処理回路25はトランジスタ
Q12〜Qzyと定電流源112を用いた2重平衡復調
回路で構成されている。一方、直流信号26はIC内の
50760Hz判別回路27より出力され、増幅器28
を経てピン23へ出力され、ピン23よりIC外部のイ
ンターフェース回路29を通してIC外部回路へ伝達さ
れる。50/60)iz判別回路27は、テレビジョン
方式のPAL。
In this figure, an AC signal 21 is applied to a pin 23 of an IC 22 via a capacitor C1l, and is passed through a buffer circuit 24 to a chroma signal processing circuit 25.
supplied to The buffer 1 circuit 24 is a transistor Qll.
and its emitter ground Il
The AC signal 21 is input from the pin 23 to the base of the transistor Q1t, and is supplied from the emitter of the transistor Qll to the next stage chroma signal processing circuit 25 through the capacitor C12. In this case, the buffer 1 circuit 24
The chroma signal processing circuit 2 cuts off the DC component and only outputs the AC signal.
5. The chroma signal processing circuit 25 is composed of a double balanced demodulation circuit using transistors Q12 to Qzy and a constant current source 112. On the other hand, the DC signal 26 is output from the 50760Hz discrimination circuit 27 in the IC, and is sent to the amplifier 28.
The signal is output to pin 23 via pin 23, and is transmitted from pin 23 to an external circuit of the IC through an interface circuit 29 external to the IC. 50/60) The iz discrimination circuit 27 is a PAL television system.

NTSC,SECAM等、すべての方式に対処したビデ
オ・クロマ回路用ICを構成した場合!I PAL受信
か、NTSC受信か、SECAM受信かという判定を行
う回路が必要であり、フィールド周波数、(50Hz若
しくは60’Hz)を検出して50)Izで、あればS
 ECAM受信である等の判定を得、その判定結果に応
じて各種回路を各テレビジョン方式に合うように切り換
えるだめの直流レベル信号を出力する。即ち、5076
0Hz判別回路27は、50Hzと60Hzとで異なる
直流レベルを出力する回路である。増幅器28は、トラ
ンジスタQ18ヲ用いたエミッタ接地形回路で構成され
ている。外部インターフェース回路29は、トランジス
タQ19を用いそのベースに抵抗分割回路及びコンデン
サを配して構成されており、外部回路に適合した電圧レ
ベルを得るための回路である。
When configuring a video chroma circuit IC that supports all systems such as NTSC and SECAM! A circuit is required to determine whether it is PAL reception, NTSC reception, or SECAM reception, and it detects the field frequency (50Hz or 60'Hz) and if it is 50) Iz, then S
It determines whether ECAM reception is being received, and outputs a DC level signal to switch various circuits to suit each television system according to the determination result. That is, 5076
The 0Hz discrimination circuit 27 is a circuit that outputs different DC levels at 50Hz and 60Hz. The amplifier 28 is constituted by a grounded emitter circuit using a transistor Q18. The external interface circuit 29 is constructed using a transistor Q19 with a resistor divider circuit and a capacitor arranged at its base, and is a circuit for obtaining a voltage level suitable for the external circuit.

上記のように構成した回路では、直流信号26はビン2
3を通して出力されると同時に、ビン23の直流電位が
変化してもバッファ回路24によりその直流電位の変化
が遮断されるので、交流信号21はビン23.バッファ
回路24を介して従来例第3図の交流信号入力回路(ク
ロマ信号入力回路)と同様に、クロマ信号処理回路25
へ供給することができる。即ち、ビン23とクロマ信号
処理回路25との間にバック7回路24を設けることに
よって、従来2つの入出力ピンが必要であったが、1つ
のビンで全く同一の機能を実現できる。
In the circuit configured as above, the DC signal 26 is
Even if the DC potential of the bin 23 changes at the same time as the AC signal 21 is output through the bin 23.3, the buffer circuit 24 blocks the change in the DC potential. Similar to the conventional AC signal input circuit (chroma signal input circuit) shown in FIG.
can be supplied to That is, by providing the back 7 circuit 24 between the bin 23 and the chroma signal processing circuit 25, the same function can be realized with one bin, whereas conventionally two input/output pins were required.

槙2図は本発明の他の実施例を示す回路図である。この
実施例は、第3図の交流信号入力回路(クロマ信号入力
回路)と直流信号入力回路(ミュート信号入力回路)の
2つの入出力回路を1つのピン使用で実現した回路例を
示している。
Figure 2 is a circuit diagram showing another embodiment of the present invention. This example shows a circuit example in which two input/output circuits, the AC signal input circuit (chroma signal input circuit) and the DC signal input circuit (mute signal input circuit) shown in Fig. 3, are realized by using one pin. .

この図において、交流信号31はコンデンサCnを介し
てIC32のビン33に加えられ、このビン33を通じ
、バッファ回路34を介してクロマ信号処理回路35へ
供給される。バッフ1回路34はトランジスタQ21 
、定゛4流源I21及びコンデンサC21で構成され、
クロマ信号処理回路35はトランジスタQ22〜Q27
と定電流g I22を用いた2重平衡復調回路で構成さ
れている。直流信号36はトランジスタQ28を用いた
増幅器37を経てビン33に加えられ、ビン33よりト
ランジスタQ29 、 Qaoを用いた差動増幅器38
及びトランジスタQ31を用いた増幅器39を経てミュ
ート回路40へ供給される。ミュート回路40はビデオ
ミエートを行うだめの回路である。
In this figure, an alternating current signal 31 is applied to a bin 33 of an IC 32 via a capacitor Cn, and is supplied through this bin 33 to a chroma signal processing circuit 35 via a buffer circuit 34. Buffer 1 circuit 34 is transistor Q21
, consisting of a constant 4-current source I21 and a capacitor C21,
The chroma signal processing circuit 35 includes transistors Q22 to Q27.
It consists of a double balanced demodulation circuit using a constant current g I22. The DC signal 36 is applied to the bin 33 via an amplifier 37 using a transistor Q28, and from the bin 33 it is applied to a differential amplifier 38 using transistors Q29 and Qao.
and is supplied to a mute circuit 40 via an amplifier 39 using a transistor Q31. The mute circuit 40 is a circuit for video conferencing.

第2図の実施例も、第1図の実施例の場合と全く同様に
、ビン33とクロマ信号処理回路35間に設けたバッフ
1回路340作用により、1つのビン33から交流信号
31と直流信号36をIC32内の各機能回路へ入力す
ることができる。
In the embodiment shown in FIG. 2, just like the embodiment shown in FIG. Signal 36 can be input to each functional circuit within IC 32.

尚、第1図及び第2図の各実施例ともIC内部の交流信
号回路がクロマ信号処理回路で、直流信号回路が50/
60Hz判別回路又はミュート回路である場合について
述べているが1本発明はこれら実施例に示した回路に限
定されることなく、一般的に、IC内に機能ごとに構成
された交流信号回路及び直流信号回路へ交流は号をビン
入力する一方直流信号をピン入力又はビン出力させるこ
とを可能とした集積回路に対して応用することができる
In each of the embodiments shown in FIGS. 1 and 2, the AC signal circuit inside the IC is a chroma signal processing circuit, and the DC signal circuit is a
Although the case where the circuit is a 60Hz discrimination circuit or a mute circuit is described, the present invention is not limited to the circuits shown in these embodiments, but generally applies to AC signal circuits and DC signal circuits configured for each function in an IC. It can be applied to an integrated circuit that allows an AC signal to be input into a signal circuit, while a DC signal can be input to or output from a pin.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、1つのビンで交流信
号の入力と直流信号の入力又は出力を行うことが可能と
なり、ICのピン数を削減できる。
As described above, according to the present invention, it is possible to input an AC signal and input or output a DC signal using one bin, and the number of pins of an IC can be reduced.

従って−例えば1チツプ内に多機fiヒで高集積化した
回路を構成することが可(1ごとなる。
Therefore, for example, it is possible to configure a highly integrated circuit with multiple devices in one chip (one chip at a time).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の集積回路の入出力回路の一実施例を示
す回路図、第2図は本発明の他の実施例を示す回路□□
□、第3図は従来の集積回路の入出力回路を示す回路図
である。 21.31・・・交流信号、22.32・・・IC。 23 .33・・・ビン、     24.34・・・
バッファ回路。 25.35・・・クロマ信号処理回路。 26.36・・・直流信号。 27−50760 Hz判別回路− 40・・・ミュート回路。
FIG. 1 is a circuit diagram showing one embodiment of an input/output circuit of an integrated circuit according to the present invention, and FIG. 2 is a circuit diagram showing another embodiment of the present invention.
□, FIG. 3 is a circuit diagram showing an input/output circuit of a conventional integrated circuit. 21.31...AC signal, 22.32...IC. 23. 33...bin, 24.34...
buffer circuit. 25.35...Chroma signal processing circuit. 26.36...DC signal. 27-50760 Hz discrimination circuit-40...Mute circuit.

Claims (1)

【特許請求の範囲】 交流信号を入力し信号処理する交流信号処理回路と直流
信号を入力又は出力する直流信号回路とが構成された集
積回路と、 この集積回路に設けられ、前記交流信号を入力すると共
に前記直流信号を前記直流信号回路へ入力又は前記直流
信号回路より出力するための1つのピンと、 このピンと前記交流信号処理回路との間に設けられ、前
記ピンへ入力された交流信号の直流成分を遮断し交流成
分のみを前記交流信号処理回路へ伝達するためのバッフ
ァ回路とを具備したことを特徴とする集積回路の入出力
回路。
[Scope of Claims] An integrated circuit configured with an AC signal processing circuit that inputs an AC signal and processes the signal, and a DC signal circuit that inputs or outputs a DC signal; and one pin for inputting the DC signal to the DC signal circuit or outputting it from the DC signal circuit, and a DC signal provided between this pin and the AC signal processing circuit, and a DC signal input to the pin. An input/output circuit for an integrated circuit, comprising a buffer circuit for blocking alternating current components and transmitting only alternating current components to the alternating current signal processing circuit.
JP19427885A 1985-09-02 1985-09-02 Input/output circuit for integrated circuit Pending JPS6254457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19427885A JPS6254457A (en) 1985-09-02 1985-09-02 Input/output circuit for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19427885A JPS6254457A (en) 1985-09-02 1985-09-02 Input/output circuit for integrated circuit

Publications (1)

Publication Number Publication Date
JPS6254457A true JPS6254457A (en) 1987-03-10

Family

ID=16321950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19427885A Pending JPS6254457A (en) 1985-09-02 1985-09-02 Input/output circuit for integrated circuit

Country Status (1)

Country Link
JP (1) JPS6254457A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005117000A (en) * 2003-09-19 2005-04-28 Sharp Corp Electrostatic protection circuit and high frequency circuit apparatus having same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005117000A (en) * 2003-09-19 2005-04-28 Sharp Corp Electrostatic protection circuit and high frequency circuit apparatus having same

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