JPS6253834B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing circuit having two systems of RAM, such as a character display device.

FIG. 1 is a block diagram showing an example of a conventional character display device using a clock signal generation circuit. It mainly consists of a memory circuit 2 (hereinafter referred to as ROM) that stores system operating procedures (programs), a memory circuit 6 (hereinafter referred to as RAM) that stores temporary data during system operation, and a memory circuit 6 (hereinafter referred to as RAM) that stores system operating procedures (programs). A character display drive circuit 7 that generates signals for display, a central processing circuit 1 (hereinafter abbreviated as CPU) that controls and processes these, and a basic clock signal from an oscillation circuit 3 are input,
A clock signal generation circuit 4 that supplies a clock signal to the CPU 1, a timing signal generation circuit 8 that generates a timing signal for character display, and a timing signal that is supplied from the timing signal generation circuit 8 via a timing signal path 11. It consists of a switch circuit 5 which alternately switches an address signal supplied from the CPU 1 via an address bus 10 and supplies it to the RAM 6. Note that 9 is a data bus for exchanging data with the CPU 1, and 12 is an output terminal of the character display drive circuit 7.

FIG. 1 shows an example using a display method tentatively named the _φ2 cycle steal display method, which can always display characters on the display. φ ₂ cycle steal display method As shown in Figure 2, CPU1
The operation of _φ1 clock signal a (1 in Figure 2) outputs an address signal with a delay of T ₁ hour (3 in Figure 2), and the _φ2 clock signal b (2nd
This method effectively utilizes the fact that the data signal (4 in Figure 2) is exchanged at the falling edge of ₂₎ in the figure, and the RAM ₆ is This method is disconnected from the address bus of the CPU 1 and uses a timing signal from a timing generation circuit 8 to extract data from the RAM 6 and display characters.

Next, the general operation shown in FIG. 1 will be explained for the case where characters are displayed according to a program stored in the ROM 2.

The CPU 1 uses an address signal to take in a character data signal to be displayed from the ROM 2 into the CPU 1, and then outputs an address signal corresponding to the position where the character is to be displayed and the previously taken character data signal. The switch circuit 5 is switched by the _φ2 clock signal b, and as shown in FIG. 2, the CPU 1 and the RAM 6 are connected during the _T3 period. Therefore, the character data signal is written into the RAM 6 by the CPU 1 during the _T3 period. In this way, character data signals are written into the RAM 6 one after another during the _T3 period. On the other hand, as shown in FIG. 2, the switch circuit 5 is switched to the opposite position from the state shown in FIG. 1 during the _T2 period, so the timing signal generation circuit 8 and the RAM 6 are connected during this period. . Therefore, the character data signal stored in RAM6 is
It is read out one after another by the timing signal during the T ₂ period, is outputted from the output terminal 12 as a character display signal via the character display drive circuit 7, and is sent to a display device such as a picture tube (hereinafter abbreviated as CPT) (not shown). Is displayed. In this way, the switch circuit 5 is alternately switched by the _φ2 clock signal b, and the CPU ₁ to RAM 6
Characters can always be displayed on the CRT screen by using the _φ2 cycle steal method, which writes data to the CRT and reads data using timing signals.

However, the character display device according to the prior art described above has the following drawbacks. Now per line on CRT screen
To display 120 characters, the CRT's horizontal repetition cycle is approximately 64 μs, so the above 1 character display period T ₄
is expressed by the following equation.

T ₄ = 64×10 ⁻⁶ /120≒530×10 ⁻⁹ (sec) = 530 (ns) Therefore, RAM6 is within T ₄ /2 period, i.e.
It must be possible to read and write within 265ns. CPU1 must also be able to operate in T ₄ hours, that is, it must be able to operate at approximately 2MHz. However, the MOS LSI currently on the market
The read time of RAM is 300 to 400 ns, and RAM faster than this is extremely expensive and special. Similarly, MOS LSIs currently on the market
The operating frequency of the CPU is 1MHz, and CPUs that can operate at 2MHz are expensive and special. As described above, character display devices using conventional clock signals have the drawback of requiring expensive and special high-speed RAM and high-speed CPU.

FIG. 3 shows another character display device using a conventional clock signal generation circuit which has improved this drawback. As is clear from a comparison with FIG. 1, in this example, two address switch circuits 13 and 14 are used as switch circuits, and the first RAM is used as RAM.
15 and a second RAM 16, and two data switch circuits 17 and 18 are added. The address switch circuits 13, 14 and data switch circuits 17, 18 are switched by the RAM switching signal c from the clock signal generating circuit 4.

FIG. 4 shows an example of the clock signal generating circuit 4 described above. As shown in FIG. 5, the clock signal generating circuit 4 generates a _φ1 clock signal a (8 in FIG. 5) which is supplied to the CPU 1 by the basic clock signal d (6 in FIG. 5) from the oscillation circuit 3. ) and _φ2 clock signal b (9 in FIG. 5), and further generates φ
₁ , _φ2 A RAM switching signal c (7 in FIG. 5) having a cycle twice that of the 2 clock signal is generated. Address switch circuits 13, 14 and data switch circuits 17, 18 are switched to the positions shown in FIG. 3 during the period when the RAM switching signal c is input. Therefore, since the first RAM is connected to CPU1, reading and writing from CPU1 is possible, and the first RAM is connected to CPU1.
Since the 2RAM is connected to the timing signal generation circuit 8 and the character display drive circuit 7, the character data signal stored in the 2nd RAM is read out and displayed. Conversely, during the period when the RAM switching signal c is not input, the address switch circuit 1
3, 14 and data switch circuits 17, 18 are switched to positions opposite to those of FIG.

As a result, the second RAM is connected to CPU1.
It becomes possible to read and write from CPU1, while
1RAM is connected to the timing signal generation circuit 8 and the character display drive circuit 7, and character data signals stored in the first RAM are read out and displayed.
In other words, as shown in Figure 5, the first RAM
During the period when the second RAM is connected to the CPU 1, a character display signal is obtained from the second RAM, and conversely, during the period when the second RAM is connected to the CPU 1, a character display signal is obtained from the first RAM.

Therefore, within one character display period _T4 , the first RAM,
It is only necessary to be able to read data from the second RAM. As shown in the above example, if 120 characters are displayed per line on the CRT screen, the one character display period _T4 is 530 ns. Therefore, the first RAM
15. As the second RAM 16, a low-cost MOS with a readout time of 300 to 400 ns, which is currently commercially available, can be used.
It becomes possible to use LSI RAM.

However, the character display device using the above-mentioned conventional clock signal generation circuit has the following drawbacks. That is, in the clock signal generation circuit 4 shown in FIG. 4, the φ ₁ and φ ₂ clock signals a and b are
T is ₄ cycles. As shown in the example above, if 120 characters are displayed per line on the CRT screen, the one character display period _T4 is 530ns, and the CPU1 is approximately 2MHz.
must be able to operate. Therefore, as mentioned above with regard to Figure 1, it is not possible to use the currently commercially available MOS LSI CPUs that operate at 1MHz, and an expensive and special CPU that operates at 2MHz cannot be used.
It had the disadvantage of having to use the CPU.

In addition, as shown in FIG. 5, the first RAM 15
is connected to CPU1, CPU1 is
2Unable to read or write to RAM16,
Similarly, when the second RAM 16 is connected to the CPU 1, the CPU 1 cannot read from or write to the first RAM 15. That is, since the relationship between the _φ1 and _φ2 clock signals a, b and the RAM switching signal c is uniquely defined, the CPU 1 cannot freely access the two RAMs. Therefore, it is necessary to create a program in advance so that the above inconvenience does not occur.
It also had the disadvantage of being difficult to program.

The purpose of the present invention is to eliminate the drawbacks of the prior art described above, and to use the general-purpose technology currently available on the market.
Provides an arithmetic processing unit that has a clock signal generation circuit that can use RAM and a CPU, and can freely access two systems of RAM without being subject to the restrictions on program creation as described above. It's about doing.

In order to achieve the above object, the present invention has a circuit configuration including a clock signal generation circuit that alternately switches the first and second RAMs at a constant cycle and stretches the clock signal supplied to the CPU depending on the RAM to be accessed. did. That is, the first configuration method is to compare the RAM switching signal with the lowest address signal of the address signals supplied to the RAM, and when the CPU and the RAM to be accessed are not connected, the clock signal that is supplied to the clock signal generation circuit is determined. The configuration includes a CPU clock signal generation circuit that cuts off the basic clock signal sent to the CPU and stretches the clock signal sent to the CPU. In addition, as a second configuration method, instead of cutting off the basic clock signal as in the first circuit configuration method, when the CPU and the RAM to be accessed are not connected, the clock signal generation circuit is inverted. It has a circuit configuration that controls the operation.

FIG. 6 is a clock signal generation circuit diagram showing one embodiment of the present invention. Its operation will be explained with reference to FIGS. 3 and 7. In FIG. 6, 21 is a flip-flop circuit that generates a RAM switching signal c (13 in FIG. 7) based on the basic clock signal d (12 in FIG. 7) from the oscillation circuit 3;
The lowest address signal e (14 in Figure 7) of the address signals from the CPU and the RAM switching signal c
An exclusive OR circuit 24 performs a comparison with φ
_An OR circuit 25 performs an OR operation between the clock signal b (17 in FIG. 7) and the output signal of the exclusive OR circuit 23; gate circuit 22 supplies the CPU with _φ1 and φ
This is a flip-flop circuit that generates _two clock signals a (16 in FIG. 7) and b. In this embodiment, the first RAM 15 is accessed by an odd address signal (the lowest address signal e is 1),
It is assumed that the second RAM 16 is accessed by an even address signal (the lowest address signal e is 0).

The present invention will be explained using a character display circuit using the _φ2 cycle steal display method described above. That is,
Reading and writing from the CPU 1 to the first or second RAM 15, 16 is performed only during the period when the _φ2 clock signal b is input. address switch circuit 13,
14 and data switch circuits 17 and 18,
During the period when the RAM switching signal c is input, the position is switched to the position shown in FIG. 3. At this time, as shown in FIG. 7, the first RAM is connected to the CPU 1, but since it is a φ ₁ clock signal period,
Reading and writing from CPU1 is not possible. on the other hand,
Since the second RAM is connected to the timing signal generation circuit 8 and the character display drive circuit 7, the character data stored in the second RAM is read out.

Further, during a period when the RAM switching signal c is not input, the address switch circuits 13 and 14 and the data switch circuits 17 and 18 are switched to positions opposite to those shown in FIG. That is, the second RAM 16 is connected to the CPU ₁ , and at this time, as shown in FIG. It is connected to the character display drive circuit 7.
1Character data signals stored in RAM are read.

As long as the above operations are repeated, only the second RAM will be connected to the CPU 1 when the _φ2 clock signal b is input, and the first RAM cannot be read or written from by the CPU 1.

Next, the RAM switching signal c is input and the
1RAM15 is connected to CPU1, and CPU1 is
The operation of the clock signal generation circuit shown in FIG. 6 when one RAM is accessed will be explained.

When the RAM switching signal c is input, the 7th
As shown in the figure, CPU1 receives _φ1 clock signal a.
is input, and the RAM switching signal c becomes 1. Then, the CPU 1 accesses the first RAM 15, but in the conventional example, as shown in FIG. 7, when the first RAM is in the CPU period, the _φ2 clock signal 18 is always at a low level, and the CPU
1RAM cannot be accessed.

Therefore, in the present invention, the _φ2 clock signal b is
Extended as shown in Figure 17, CPU of 1st RAM 15
The _φ2 clock signal is output during this period. Therefore, during the period when the RAM switching signal c is input, the output signal of the exclusive OR circuit 23 is not active (output signal "1"), and since the _φ2 clock signal b is also 0, The OR circuit 24 does not become active (output signal "1"). Therefore, while the RAM switching signal c is being input, the basic clock signal d is not outputted from the gate circuit 25 as the output f, as shown in FIG. 7. Therefore, as shown in FIG. 7, the φ ₁ clock signal a is not inverted, and the φ ₂ clock signal a is not inverted.
Clock signal b is not output. But then
During a period in which the RAM switching signal c is not output, the output signal of the exclusive OR circuit 23 becomes active (output signal "1"), and the OR circuit 24 becomes active (output signal "1").

Therefore, the basic clock signal d is the gate circuit 2.
5 and is input to the flip-flop circuit 22 as a signal f. Therefore, when the RAM switching signal c is input again, the flip-flop circuit 22
is inverted, and the _φ2 clock signal b is output. φ
When _{the second} clock signal b is output, the first RAM 15
is connected to CPU1, so it can be read and written by the CPU.

When accessing the RAM connected to the CPU 1 while the _φ1 clock signal a is being input in this way, the gate circuit 25 is used to remove one basic clock signal d to stretch the _φ1 clock signal, and then try to access again
When RAM and CPU1 are connected, a _φ2 clock signal is output, allowing reading and writing from the CPU.

In addition, as shown in Figure 7 16 and 17, CPU1
The period of the φ ₁ and φ ₂ clock signals a and b supplied to the φ 1 and φ 2 clock signals a and b is twice the one-character display period T ₄ . As shown in the example above, when displaying 120 characters on a CRT screen, the display period for one character _T4 is approximately 530ns, so
The CPU 1 only needs to operate at approximately 1 MHz, and any inexpensive MOS LSI CPU currently available on the market can be used. Furthermore, reading and writing from the RAM may be performed in the _T4 period, and general-purpose RAMs currently available on the market with read/write times of 300 to 400 ns can be used.

FIG. 8 is a clock signal generation circuit diagram showing a reference example. Its operation will be explained with reference to FIGS. 3 and 9. The same reference numerals in FIG. 8 as in FIG. 6 represent the same parts. 28 is the lowest address signal e (22 in Figure 9) of the address signals from the CPU.
The exclusive OR circuit 26 for comparison with the RAM switching signal c (21 in FIG. 9) is inverted by the basic clock signal d (20 in FIG. 9),
_φ1 and _φ2 clock signals a supplied to the CPU
(24 in FIG. 9) and a flip-flop circuit that generates b (25 in FIG. 9), 27 is a logic circuit of the _φ1 clock signal a, the output signal of the exclusive OR circuit 28, and the basic clock signal d. The product g (23 in FIG. 9) is output and the flip-flop circuit 2
6, and its output is connected to the set terminal of the flip-flop circuit 26. Further, as in the embodiment shown in FIG. 6, the first RAM 15 is accessed by an odd number address signal (the lowest address signal e is 1), and the second RAM 1
6 is accessed by an even address signal (the lowest address signal e is 0).

The operation in this case will be explained using a character display circuit using the _φ2 cycle steal display method as in the previous embodiment. As described above regarding the first embodiment, φ ₁ ,
If _{the φ2} clock signal is constant, as can be seen from FIG.
2 RAM 16, and the first RAM 15 cannot be read or written from by the CPU 1.

RAM switching signal c is input, and the first RAM1
When 5 is connected to CPU1, CPU1 is the first RAM
The operation of the clock signal generation circuit when the clock signal is accessed will be explained.

When the RAM switching signal c is input, the 9th
As shown in the figure, the φ1 clock signal a is input to the CPU ₁ , and the lowest address signal e becomes 1. Therefore, during the period when the RAM switching signal c is being input, the output signal of the exclusive OR circuit 28 is not active (output signal "0"), and therefore the output of the logic circuit 27 is an inverted control signal. g (9th
23) in the figure is output. By inputting this inversion control signal g to the set terminal of the flip-flop circuit 26, the circuit 26 is not inverted even though the basic clock d is input, and the next RAM switching signal c is not input. The period also
_φ2 clock signal b is not output. However, during the period when this RAM switching signal c is not input, the output signal of the exclusive OR circuit 28 becomes active (output signal "0"), and the inverted control signal g is not output to the output of the logic circuit 27. Become. Therefore, when the RAM switching signal c is input again and the first RAM 15 and the CPU 1 are connected, the flip-flop circuit 26 is inverted by the basic clock signal d, and the _φ2 clock signal b is output. In this way, when the first RAM 15 is connected to the CPU 1, the _φ2 clock signal is output, so
The CPU 1 can read and write to the first RAM 15.

As described above, when accessing the RAM connected to CPU 1 while the _φ1 clock signal a is being input, the _φ1 clock signal is extended by controlling the inversion operation of the flip-flop using the inversion control signal. Then, when the RAM to be accessed again is connected to the CPU 1, a _φ2 clock signal is output, allowing reading and writing from the CPU.

Similar to the previous embodiment, and 24-2 in FIG.
7, the period of the _φ1 and _φ2 clock signals a and b supplied to the CPU 1 is one character display period.
It is twice that of _T4 . As shown in the previous example,
When displaying 120 characters on a CRT screen, one character display period _T4 is approximately 530ns, so CPU1 is approximately 1MHz.
Cheap MOS currently available on the market that works with
Can use LSI CPU. Also RAM
It is sufficient to read and write in T ₄ period, and the reading and writing time of currently available on the market is 300 ~
400ns of general-purpose RAM can be used.

In the reference example shown in FIG. 8, an inverted control signal g is obtained using the _φ1 clock signal a, and this is input to the set terminal of the flip-flop circuit 26. However, it is possible to obtain the same effect as this embodiment with a clock signal generation circuit configured to obtain an inverted control signal using the _φ2 clock signal b and input it to the reset terminal of the flip-flop circuit. It should be obvious.

The present invention provides an expensive, specialized system that uses only a few circuit components and operates at very high speeds.
It is possible to configure an arithmetic processing device that can freely access two systems of RAM without the need to use a CPU or RAM, and without any restrictions on program creation. i.e. 120 on the CRT screen
When displaying characters, if a conventional clock signal generation circuit is used, a CPU that can operate at 2MHz or a RAM that can read and write at 260ns is required.
is required, and the general-purpose 1MHz currently available on the market
A CPU that runs on
It was not possible to use RAM, making it a very expensive device. However, according to the present invention, the CPU
It only needs to be able to operate at 1MHz, and the RAM only needs to have a read/write time of 530ns or less. Therefore, the general-purpose and inexpensive
A CPU and RAM can be used, and an inexpensive arithmetic processing device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a character display device using a conventional clock signal generation circuit.
Figure 2 shows the CPU clock signal in Figure 1,
A diagram showing the relationship between address signals and data signals,
FIG. 3 is a block diagram showing an example of a conventional character display device using two systems of RAM, FIG. 4 is a block diagram showing an example of a clock signal generation circuit according to the prior art, and FIG. RAM switching signal, CPU clock signal, and 1st and 2nd RAM in Figure 4
FIG. 6 is a block diagram of the first embodiment of the clock signal generation circuit according to the present invention, and FIG. 7 shows the RAM switching signal when the clock signal generation circuit of FIG. 6 is used. A diagram showing the relationship between the CPU clock signal and the connection state of the first and second RAMs, FIG. 8 is a block diagram of a reference example of the clock signal generation circuit according to the present invention, and FIG. 9 is a diagram showing the relationship between the CPU clock signal and the connection state of the first and second RAMs. FIG. 3 is a diagram showing the relationship between the RAM switching signal, the CPU clock signal, and the connection state of the first and second RAMs when 1...CPU, 2...ROM, 4...Clock signal generation circuit, 8...Timing signal generation circuit, 1
3, 14...address switch circuit, 15...th
1RAM, 16...second RAM, 17, 18...data switch circuit, 21, 22, 26...flip-flop circuit.

Claims (1)

[Claims] 1. First and second storage circuits that store data;
An address switch circuit that alternately connects the first and second memory circuits to the central processing circuit according to the lowest address signal; a memory circuit switching signal that is supplied to and controls the address switch circuit; and a central processing circuit. An arithmetic processing device comprising a clock signal generation circuit that generates first and second clock signals to be supplied to a processing circuit, wherein the clock signal generation circuit generates a storage circuit switching signal that is inverted by a third clock signal. a switching signal generation circuit that generates a switching signal; a comparison circuit that compares the lowest address signal of the address signals from the central processing circuit with the storage circuit switching signal; a gate circuit that is supplied with the third clock signal; a signal generation circuit for the central processing circuit that generates first and second clock signals having different phases that are inverted by the output signal of the gate circuit and supplied to the central processing circuit; 1. An arithmetic processing device comprising: an OR circuit that controls the gate circuit by ORing with a clock signal of 1.