JPS6252972A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the capacitance between a control gate and a floating gate and reduce the occupying area of a memory cell by a method wherein grooves are formed in passive regions of a semiconductor substrate and the floating gate and the control gate are extended into the grooves. CONSTITUTION:An active region is formed on a semiconductor substrate and, in predetermined regions in the active region, a source 6 and a drain 7, composed of impurity diffused layers, of a memory transistor and a bit line 5 are formed. Grooves 15 and 16 are formed in passive regions of the semiconuductor substrate, which are formed on both sides of the active region. A floating gate 2 and a control gate 1 are so formed as to extended into those grooves 15 and 16. Moreover, an insulating film region (tunnel region 4), whose film thickness is smaller than the thickness of other insulating films (gate insulating films) is formed in the predetermined region between the floating gate 2 and the drain 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in the structure of a semiconductor memory device, particularly a nonvolatile semiconductor memory device that can be rapidly written/erased.

[Prior Art] FIG. 4 is a diagram showing a planar arrangement of a conventional nonvolatile semiconductor memory device. In FIG. 4, a memory cell of a semiconductor memory device includes a source 6 and a drain 7 of a memory transistor, each formed of an impurity diffusion layer, and a pit line 5 for reading information held by the memory transistor. Further, a 70-ting gate 2 for accumulating charges in a U-shape is formed so as to sandwich the drain 7 (active region), and the 70-ting gate 2 is further overlapped with the floating gate 2 with an insulating film interposed therebetween. Control gate 1 for controlling charge accumulation and release of
is formed. A tunnel region 4 is provided between the floating gate 2 and the drain 7 to serve as a path for charges. This tunnel region 4 is a region composed of a thin i8 green film with a thickness of about 100 A, a floating gate 2, and a drain 7. Further, a word line 3 for selecting this memory transistor is provided so as to intersect with the bit line 5 and the drain 7 via an insulator.

FIG. 5 is a diagram schematically showing a cross-sectional structure of a memory cell of the nonvolatile semiconductor memory device shown in FIG. 4. As seen from FIG. 5, the memory cell is composed of two \10S type transistors forming a memory transistor section and a select transistor section, respectively.

The memory transistor includes a source 6 and a drain 7 formed in an active region of a semiconductor substrate 50, and a source 6 and a drain 7 formed in an active region of a semiconductor substrate 50.
It consists of an upper floating gate 2 and a control gate 1.

The select transistor is composed of a source (shared with the drain of the memory transistor) 7 and a bit line 5 formed in the active region of the semiconductor substrate 50, and a word line 3 on the semiconductor substrate 50.

Source 6, control gate 1 and bit line 5
are respectively source electrodes 8. The control game is connected to the power source 9 and the pit line electrode 11.

Also, between the floating gate 2 and the semiconductor substrate 50 and between the floating gate 2 and the control gate 1
There is H! i Since a green film is provided, the capacitance between the control gate and the floating gate is 12
, a floating gate-to-semiconductor substrate capacitance ff113, and a floating gate-to-drain capacitance 114 of the memory transistor. The floating gate 2 is surrounded by an insulator and is electrically floating. Next, the operation will be explained.

First, writing 111f to this memory cell will be explained. At this time, the source electrode 8 is electrically floating,
The control gate electrode 9 is set to a ground potential, the word line electrode 10 is set to a high voltage, and the pit line electrode 11 is set to a high voltage. In this state, both the bit line 5 and the word line 3 are at a high voltage, so the potential at the drain 7 of the memory transistor is at a high voltage. As a result, the potential difference between the control gate 1 and the drain 7 becomes a dog, and a high electric field also exists in the tunnel region 4 due to the parasitic capacitance l formed between the control gate, the drain 7, and the semiconductor substrate 50, or due to the capacitance division of the circuit. is applied, and a tunnel current flows from the floating gate 2 to the drain 7. As a result, electrons are extracted from the floating gate 2, and the threshold voltage of the memory transistor is shifted to the lower side, making it a deresion mode transistor.

Therefore, when the control gate 1 is set to the ground potential when reading information held by the memory transistor, the memory transistor is turned on.

Next, the erase operation will be explained. At this time, the source electrode 8 is set to a ground potential, the control gate electrode 9 is set to a high voltage, the word line electrode 10 is set to a high voltage, and the pit line electrode 11 is set to a ground potential.

In this state, the bit line 5 is at ground potential and the word line 3 is at a high voltage, so the drain 7 is at ground potential. As a result, drain 7 and control gate 1
The potential difference becomes large between, and a high electric field is also applied to the tunnel region 4 due to the capacitance M (capacitance division of the capacitive circuit formed by the parasitic capacitance between the control gate 1 and the drain 7° semiconductor substrate 50). A tunnel current flows from the drain 7 to the floating gate 2. As a result, electrons are accumulated in the floating gate 2, and the threshold voltage of the memory transistor shifts to a higher side, making it an enhancement type transistor. Therefore, when reading data, when the control gate 1 is set to the ground potential, the memory transistor is turned off.

Information 111N, "0" is stored depending on the on/off state of this memory transistor.

Next, the electric field applied to the oxide 1111 (tunnel oxide film) in the tunnel region 4 will be described.

6A and 6B show the capacitance 12 between the control gate 1 and the floating gate. floating gate
Semiconductor substrate capacitance 13F3 and floating gate
2 is a diagram showing a capacitive circuit formed by an inter-drain capacitor 14. FIG. FIG. 6A shows the potentials of the control gate, source and drain during writing, and FIG. 6B shows the state during erasing operation. The electric field applied to the oxide film (tunnel oxide film) in the tunnel region 4 during writing and erasing will be described below with reference to FIGS. 6A and 6B. Now the capacitance between control gate and floating gate is 12
The capacitance of the floating gate-to-semiconductor substrate capacitor 13 is C2,70, the capacitance of the floating gate-drain capacitor 14 is 03, the thickness of the tunnel oxide film is Toxs, and the applied high voltage is VFF. . In this state, the electric field Ev applied to the tunnel region 4 during writing is
is expressed as. Further, the electric field Ee applied to the tunnel region 4 during erasing is expressed as follows. In either case, as CI (control gate-floating gate capacitance) increases, the electric field applied to the tunnel region 4 increases, the tunnel current increases, and the change l in the threshold voltage of the memory transistor increases. The large amount of change in threshold voltage has the advantage of increasing the successive margin and lengthening the data retention time.

[Problems to be Solved by the Invention] In conventional memory cells of this type, for the purpose of increasing the successive margin and data retention time,
In order to increase the control gate-floating gate capacity l, it was necessary to increase its area. This poses a problem that becomes a major bottleneck in achieving high integration.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that eliminates the above-mentioned problems and reduces the area occupied by memory cells without reducing the control gate-floating gate capacitance.

[Means for Solving the Problems] In the semiconductor memory device according to the present invention, a groove is formed in an inactive region of a semiconductor substrate, and both the floating gate and the control gate partially extend into the groove. is formed.

[Function] Even inside the formed groove, the control gate and 7
Since the floating gate and floating gate face each other with an insulating film in between, the capacitance between the control gate and the floating gate can be increased, and even if the area occupied by the memory cell is reduced, the lateral area of the trench is not large. Since there is no influence, a memory cell occupying a small area can be realized without reducing the capacitance between the floating gate and the control gate.

[Embodiments of the invention] An embodiment of the present invention will be described below.

1 to 3 are diagrams showing the configuration of a semiconductor memory device that is an embodiment of the present invention, with FIG. 1 showing a planar arrangement, and FIG. 2 along line A-A in FIG. 1. FIG. 3 is a diagram schematically showing a cross-sectional structure taken along line B-8 in FIG. 1. FIG.

In FIG. 1, an active region is first formed on a semiconductor substrate. A source 6 and a drain 7 of a memory transistor made of an impurity diffusion layer and a bit line 5 are formed in a predetermined region of this active region.

As a feature of the invention, trenches 15, 16 are formed in the inactive regions of the semiconductor substrate on both sides of the active am.

Floating gate 2. The control gate 1 is formed so as to extend into the inside of this trench 15,16. Further, as in the conventional case, an insulating film region (tunnel region) having a thickness thinner than other insulating films (gate insulating film II) is formed in a predetermined region between the floating gate 2 and the drain 7.
A tunnel oxide film 4 through which tunnel current flows is formed. Furthermore, word lines 3 are provided to intersect with the active region via an insulating film, as in the prior art.

With the above configuration, floating gate 2° control gate 1. Tunnel area 4. A memory transistor consisting of a source 6 and a drain 7 is configured. Also,
Word line 3. The source (drain of the memory transistor) 7 and the bit line 5 form a select transistor for selecting the memory transistor.

The drain of the memory transistor and the source of the select transistor are shared, thereby connecting the memory transistor and the select transistor in series.

The control gate 1 is also connected to a control gate electrode 9 as seen in FIG. Furthermore, as seen from FIG. 2, grooves 15 and 16 are formed so as to sandwich the active region (drain 7), and a control gate 1 and a floating gate 2 are formed inside the grooves with an insulating film interposed therebetween. . This increases the opposing area between the control gate and the 70-ting gate,
The capacitance between the control gate and the floating gate is increasing. Further, as seen from FIG. 3, a word line electrode 10 is connected to the word line 3, a bit line electrode 11 is connected to the bit line 5, and a source electrode 8 is connected to the source 6; It has a structure similar to that of the conventional semiconductor memory device shown in FIG.

The equalization circuit and capacitive coupling circuit of the semiconductor memory device according to the present invention have the same structure as the conventional one. However, floating gate 2. Since the control gate 1 is formed so as to extend into the grooves 15 and 16 formed in the inactive region, the control gate-floating gate interference C1 is increased compared to the conventional case. Therefore, even if the area occupied by the memory cell is reduced, the groove portion is not affected much, and a large capacitance between the floating gate and the control gate can be realized.

Therefore, from equations <1) I'3 and (2), the electric field E applied to the tunnel region 4 during writing and erasing
Both v and E6 increase, the tunnel current increases, and the amount of change in the threshold voltage of the memory transistor increases.

Note that the potential of each electrode during write and erase operations is the same as in the conventional example, but if the amount of change in the threshold voltage of the memory transistor is to be the same as in the conventional example, the value of the applied high voltage VPF should be changed. Can be made smaller. Applied high voltage Vp
Lowering r facilitates higher integration of high voltage generation circuits and the like.

[Effects of the Invention] As described above, according to the present invention, a groove is formed in an inactive region of a semiconductor substrate, and a floating gate and a 5-control gate are formed so as to extend within the groove. Since the capacitance between the control gate and the floating gate can be increased, the area occupied by the memory cell can be reduced, and the value of the high voltage VPF can also be reduced, it is possible to obtain a highly integrated semiconductor memory device. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor memory device which is an embodiment of the present invention. Figure 2 is A-All! of Figure 1! FIG. 3 is a schematic diagram showing a cross-sectional structure along the line B-B1 in FIG.
FIG. 1 is a diagram schematically showing a cross-sectional structure along line 1; FIG. 4 shows the conventional semiconductor diagram 9. FIG. 3 is a diagram showing a planar arrangement of the device. FIG. 5 is a conceptual diagram schematically showing the cross-sectional structure of a conventional semiconductor memory device. FIG. 6A and FIG. 6B are diagrams isometrically showing a capacitance circuit constituted by a parasitic capacitance of a semiconductor memory device, and FIG.
FIG. 68 shows the state during writing, and FIG. 68 shows the state during erasing. In the figure, 1 is a control gate, 2 is a floating gate, 6 is a source of a memory transistor, 7 is a drain of a memory transistor, and 15 and 16 are grooves. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A semiconductor memory device including at least one MOS type transistor formed in an active region of a semiconductor substrate, wherein the MOS type transistor is formed on the semiconductor substrate with a first insulating film interposed therebetween. a first gate that stores charge;
a second gate formed on the first gate via a second insulating film to control charge accumulation in the first gate, and formed in an inactive region of the semiconductor substrate. What is claimed is: 1. A semiconductor memory device, comprising: a groove formed into a groove, wherein at least a portion of the first gate and the second gate are both formed to extend into the groove.