JPS62523B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable sequencer having an output check function.

For conventional programmable sequencers,
The operation of its internal circuits was checked for some degree of abnormality and countermeasures were taken using the abnormality check program, but when an abnormality occurred in the output circuit, there was no way to check this, and the abnormality eventually occurred. Control continues in the same state, and when it is determined that there is an abnormality in the controlled device, an abnormality in the output circuit on the sequencer side is discovered as a result of investigation.It takes time to discover the abnormality, which can lead to a serious accident. There was a fear that it would lead to

The present invention has been provided in view of the above points, and is capable of automatically checking the presence or absence of an abnormality in the output circuit, detecting an abnormality in the output operation, and taking necessary measures such as stopping the control operation. The purpose is to provide a programmable sequencer that can perform the following steps.

An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 1 shows a configuration example of a programmable sequencer according to an embodiment of the present invention, in which an input circuit 1 receives an input signal, and the input data output from the input circuit 1 is a load signal given from a control section 6. is loaded into shift register 2 by . The shift register 2 is composed of the first to nth shift registers, and after loading the input data as described above, converts the input data into serial data using the shift clock supplied from the control unit 6 and sequentially inputs it to the storage unit 3. Then, the input signal is written and stored in this storage section 3 as input data. Next, the input data is subjected to arithmetic processing in the arithmetic unit 4 according to the program stored in the program storage part of the memory part 3, and the data resulting from the arithmetic processing in the arithmetic unit 4 is sent to the pre-storage part 3 as output data. Make me remember. When the arithmetic processing operation in the arithmetic unit 4 is thus completed, the output data read out from the storage unit 3 is sequentially sent to the shift register 2 according to the shift clock given from the control unit 6, and the transmission of this output data to the shift register 2 is performed. Upon completion, the contents of the shift register 2 are latched in the output circuit 5, and the output circuit 5 sends out the latched signal as an output signal. This is the basic operation in the circuit of FIG. 1, and is repeated continuously.Next, the configuration and operation according to the present invention will be explained. In other words, in the circuit shown in FIG. 1, the 4 bits output from input circuit 1 and the 4 bits output from output circuit 5 are connected to the input section of shift register 2, but the number of bits for each can be set arbitrarily. The output signal is thus fed back and loaded into the shift register 2 in parallel with the input data from the input circuit 1. However, when the data is taken into the storage section 3, the shift register 2 outputs the input data from the input circuit 1 or the data of the output signal from the output circuit 5 to the storage section 3. When the data of the shift register 2 is the data of the output signal, this data and the output data stored in the storage section 3 are compared in the comparison section 7, and when they match, the output circuit 5
It is assumed that there is no abnormality in the output circuit, and when a discrepancy is detected, this is outputted to the outside together with the address number of the output circuit where the abnormality has occurred, and processing such as stopping the control operation by the sequencer is performed.
Prevent serious accidents from occurring.

FIG. 2 is a more detailed circuit block diagram of the main part of the circuit of FIG. 1. Here, the storage section 3 shows only an input/output data storage section 3a and an output storage section 3b, and storage circuit parts for other programs are omitted from illustration. The input/output data storage section 3a is converted into the output storage section 3.
b is a RAM controlled by the same address, and in order to determine whether the data in the input/output data storage unit 3a at each address is input data or output data, the corresponding address part of the output storage unit 3b is An “H” or “L” signal is written into the output storage unit 3b at a certain address.
If the output OUT signal of ``H'' indicates that the data in the input/output data storage section 3a at that address is output data, and the output of the output storage section 3b on the other hand
If the OUT signal is "L", it is determined that the data in the input/output storage section 3a at that address is input data. In this way, when input data is stored in the input/output data storage section 3a of the storage section 3 via the input circuit 1 and the shift register 2, as in the circuit of FIG.
This input data is to be subjected to arithmetic processing in the arithmetic unit 4, and at the time of this arithmetic processing, the arithmetic result output of the arithmetic unit 4 is written to the input/output data storage unit 3a as output data, and at the same time, this input/output data storage An OUT signal (“H” signal) indicating that the data stored in section 3a is output data is written to output storage section 3b. When the calculation in the calculation unit 4 is completed, the data from the input/output data storage unit 3a is sent to the shift register 2 by the shift clock, and when the transmission of this data to the first to nth shift registers ₂₁ to _2o is completed, the latch is activated. A signal is generated, the contents of the shift register 2 are latched into the output circuit 5, and the output circuit 5 sends the contents to the outside as an output signal. On the other hand, the output of this output circuit 5 is also connected to the input of the shift register 2, and the output signal of this output circuit 5 is loaded into the shift register 2 by a load signal. Therefore, the signal loaded into the shift register 2 is sent back to the input/output data storage section 3a by the shift clock. At this time, OUT of the output storage section 3b
When the signal output is "L", the data sent back from the shift register 2 is input data, and at this time, the input/output data storage section 3a is controlled by the second write signal, and the input data is not written. It is done. On the other hand, when the OUT signal output of the output storage section is "H", the data sent back from the shift register 2 is the data of the output signal, and therefore the output of the input/output data storage section 3a and the shift register A comparator 7 consisting of an exclusive OR circuit 8 compares the data of the output signal sent back from the output circuit 2, and when the two do not match, an abnormality in the output circuit is detected. That is, in the circuit of FIG. 2, the exclusive OR circuit 8 outputs an L signal if the two data to be compared match, indicating a normal state, but if the two signals do not match, the exclusive OR circuit 8 outputs an L signal. 8 becomes "H", and gate circuits 9 and 10
An abnormality signal of "L" signal is outputted through. Furthermore, if the address at this time is detected, the address number of the abnormal output circuit can be identified since there is a one-to-one correspondence between the address and each output signal. Here, the above-mentioned abnormal signal is outputted only when data is taken in for which the input busy signal is at the "L" level. In the figure, reference numeral 16 denotes an address circuit which performs an address scan on the storage section 3 based on its output.

3 and 4 show different embodiments of the output circuit portion, and the circuit in FIG. 3 is an example in which the load operated by the output of the output latch 5a of the output circuit 5 is a DC load, and the circuit shown in FIG. 14 and phototransistor 15, the output signal of the output circuit 5 is transferred to the n-th shift register 2 of the shift register 2.
It is arranged so that it can be inputted by returning it to the input terminal of n.
Therefore, in the circuit of FIG. 3, even if no voltage is applied to the load circuit (not shown), this can be detected as an abnormality in the output circuit. On the other hand, in the circuit shown in FIG. 4, light emitting diodes 14 and 14a are provided which conduct in two current directions on the output side, and these are optically coupled to two phototransistors 15 and 15a connected in parallel on the input side of the shift register 2. In this case, the load is one that can be operated with either direct current or alternating current, and even if the power source is not connected to the load or the power line to the load is disconnected, this can be detected as an abnormality in the output circuit.

FIG. 5 and FIG. 6 show an example of the operating state. To simplify the explanation, let us assume that the total number of bits in shift register 2 is 12 bits,
Depending on the user's selection, 5 bits of input data and 6 bits of input data
Assuming that we are handling bit output data,
As shown in FIG. 5, 5 bits out of a total of 12 bits in the shift register 2 are connected to the input circuit 1, and 6 bits out of the remaining 7 bits are used for feedback of output data. Six bits of the output circuit 5 are connected to the output terminal of the shift register 2 corresponding to the feedback input. When the power is turned on and the program is started, the output latch 5a is cleared, so all output data fed back to the shift register 2 is 0. Therefore, in FIG. 6A, the output data of the input signal loaded into the shift register 2 is all 0. This is written to the input/output data storage section 3a of the storage section 3 in (b), and the output data is determined by arithmetic processing in (c), and the output data portion of the data stored in the input/output data storage section 3a is changed. At the same time, 1 is written to the bit corresponding to the output data portion of the output storage section 3b. This output storage section 3
b is written every time arithmetic processing is performed, but
The bit pattern remains unchanged until the end of the run. Next, in d, all the data in the input/output data storage section 3a is read out to the shift register 2, and the output data therein is latched in the output circuit 5 by the latch signal in d. At the same time, the output data from the output latch 5a is fed back to the shift register 2, and is loaded into the shift register 2 along with the input data by the load signal to the shift register 2. This shift register 2
The content of is written to the storage unit 3 in G is the same as in B above, but this time the content is written to the output storage unit 3b.
contains 1 (see broken line part A in the figure), so the broken line part B is newly written to the storage unit 3.
The data is compared with the data in the dashed line portion A, which is the original data, and if they do not match, an abnormality in the output circuit is detected.

Since the present invention is configured as described above, when an abnormality occurs in the output circuit, the fact that the abnormality has occurred and the address number of the output circuit can be immediately determined, and maintenance can be performed appropriately. This has the effect of preventing major accidents from occurring in the controlled equipment on the load side.
Also, when specifying input/output address numbers in a program, you may specify the address number as an output even though only the input circuit is connected, or vice versa, specify the input circuit to the address number to which the output circuit is connected. Even if such a problem occurs, it can be detected as an abnormality in the output circuit, and program errors can also be easily detected.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a more detailed block diagram of the main parts of the above, Fig. 3 is a circuit diagram of the main parts of the output circuit section of the above, and Fig. 4 is the output circuit of the same. FIG. 5 is a main part block diagram showing an example of the usage state of the same as above;
FIG. 6 is an explanatory diagram of the same operating state as above, in which 1 is an input circuit, 2 is a shift register, 3 is a storage section, 4 is an arithmetic section, and 5 is an output circuit.

Claims (1)

[Claims] 1 The input data received by the input circuit is converted into parallel/serial data by a shift register and written into the storage section, and the input data stored in the storage section is processed by the calculation section based on a preset program. In a programmable sequencer that temporarily stores the resulting output data in a storage section, converts the output data written in the storage section into serial/parallel data using the shift register, latches it in an output circuit, and sends out an output signal, The output data of the output circuit is fed back and loaded into the shift register together with the input data, and when writing the output of this shift register to the storage section,
Comparing the feedback output data and the output data stored in the storage unit bit by bit,
A programmable sequencer characterized in that it detects an abnormality in output operation when there is a mismatch.