JPS6250980B2 - - Google Patents
Info
- Publication number
- JPS6250980B2 JPS6250980B2 JP54170984A JP17098479A JPS6250980B2 JP S6250980 B2 JPS6250980 B2 JP S6250980B2 JP 54170984 A JP54170984 A JP 54170984A JP 17098479 A JP17098479 A JP 17098479A JP S6250980 B2 JPS6250980 B2 JP S6250980B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- conductive layer
- package
- external leads
- short
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の保護方法に関し、詳しく
は、半導体装置の組立中、試験中、運搬中、ある
いは保管中、更には、半導体装置の実装組立の準
備中、その半導体装置に塔載される、又は、すで
に塔載されている半導体素子を、静電破壊その他
の電気的な原因による破壊の危険から保護する、
半導体装置の保護方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for protecting a semiconductor device, and more specifically, the present invention relates to a method for protecting a semiconductor device, and more specifically, during assembly, testing, transportation, or storage of a semiconductor device, and furthermore, during preparation for mounting and assembling the semiconductor device. Protecting semiconductor elements mounted on equipment or already mounted on equipment from the risk of destruction due to electrostatic discharge damage or other electrical causes;
The present invention relates to a method for protecting a semiconductor device.
半導体装置は、一般に、いづれの型式にあつて
も、各端子間の降伏電圧は低く、おゝむね10V程
度以下であり、又、各端子間リード線の電流容量
も小さく、おゝむね数Ａ程度以下である。そのた
め、半導体素子をパツケージに組み込む工程にお
いて、またその素子が組み込まれた半導体装置の
試験工程において、更にその試験が完了した半導
体装置の運搬・保管の期間において、要すれば、
実装に至るまでのすべての期間中、半導体素子
は、静電気による破壊の危険や、その他の電気的
要因による破壊の危険にさらされている。 Regardless of the type of semiconductor device, the breakdown voltage between each terminal is generally low, approximately 10 V or less, and the current capacity of the lead wire between each terminal is also small, approximately a few A. It is below that level. Therefore, in the process of assembling a semiconductor element into a package, in the process of testing a semiconductor device in which the element is incorporated, and during the transportation and storage period of the semiconductor device after the test, if necessary,
During the entire period leading up to packaging, semiconductor devices are exposed to the risk of destruction due to static electricity and other electrical factors.
この危険から半導体素子を保護するため、かゝ
る危険の存する期間中、半導体装置のすべての端
子を短絡しておくことが、従来からなされてい
た。そのすべての端子を短絡するため従来から採
用されている方法としては、(イ)１枚の金属板から
櫛歯状金属片群を作り、これを切り離してリード
とすることを前提とし、組立期間中は、これを切
り離さないでおく方法、(ロ)試験中は特殊な治工具
を使用する方法、(ハ)組立・運搬・保管期間中、す
べての端子リードを金属フオイルで包んでおく方
法等があるが、いづれも、煩瑣であるとか、保護
効果が不十分であるとか、あるいは、附加的工程
を要する等、種々な不利益を避け難かつた。 In order to protect semiconductor elements from this danger, it has been conventional practice to short-circuit all terminals of the semiconductor device during the period when such danger exists. The conventional method used to short-circuit all the terminals is (a) to make a group of comb-shaped metal pieces from a single metal plate and cut them off to form leads, and the assembly time is (b) Using special jigs and tools during testing; (c) Wrapping all terminal leads in metal foil during assembly, transportation, and storage. However, it is difficult to avoid various disadvantages such as being cumbersome, having insufficient protective effects, or requiring additional steps.
本発明の目的は、かゝる不利益を解消すること
にあり、簡易であり、かつ、附加的工程を殆んど
要することなく、しかも、十分な保護効果を発揮
する、半導体装置の保護方法を提供することにあ
り、半導体装置用パツケージ製作の最終工程にお
いて、そのパツケージの外表面の一部に、蒸着あ
るいはメツキにより電導層を形成してリードのす
べてを短絡しておき、このすべてのリードが短絡
された半導体装置用パツケージに半導体素子を塔
載し、この状態で運搬・保管をなし、試験又は実
装の直前に、例えば、一般には実装の第１工程で
ある、外部リード予備はんだ工程において、前記
の電導層を除去することを要旨とし、この電導層
を除去する工程を加える前の状態において保護機
能を発揮し、又、製品として販売の対象となるも
のである。 An object of the present invention is to eliminate such disadvantages, and to provide a method for protecting a semiconductor device that is simple, requires almost no additional steps, and exhibits sufficient protection effects. In the final process of manufacturing a semiconductor device package, a conductive layer is formed on a part of the outer surface of the package by vapor deposition or plating to short-circuit all the leads. A semiconductor element is mounted on a short-circuited semiconductor device package, transported and stored in this state, and immediately before testing or mounting, for example, in the external lead pre-soldering process, which is generally the first process of mounting. , which is intended to remove the conductive layer described above, exhibits a protective function in a state before the step of removing the conductive layer, and is sold as a product.
以下、この発明に係る半導体装置の保護方法の
各工程を順次説明する。 Each step of the method for protecting a semiconductor device according to the present invention will be sequentially explained below.
第１の工程は電導層形成工程であり、半導体装
置用パツケージ製作の工程において外部リードの
取り付けがなされた後、そのリードのすべてを短
絡するように、そのパツケージ外表面の一部に電
導層を形成する。この電導層の具有する特性は、
(イ)セラミツク・樹脂等のパツケージ材と密着し、
(ロ)はんだ濡れ性がよく、(ハ)半導体装置の試験又は
実装に先立ち電導層の除去を必要とするときは、
容易に除去しうるものであり、(ニ)電導層としての
比抵抗が109-10オーム・センチメートル程度以下
であることである。したがつて、この電導層形成
方法には大きな自由度があり、(イ)金・銀・銅・
錫・鉛・鉛／錫・インジユーム等の金属を蒸着す
る方法、(ロ)金・銀・銅等上記の金属を無電解メツ
キする方法がある。 The first step is a conductive layer forming step. After the external leads are attached in the process of manufacturing a semiconductor device package, a conductive layer is formed on a part of the outer surface of the package so as to short-circuit all of the leads. Form. The characteristics of this conductive layer are:
(a) Closely adheres to package materials such as ceramics and resin,
(b) Good solder wettability and (c) When the conductive layer needs to be removed prior to testing or mounting the semiconductor device,
It must be easily removable and (d) have a specific resistance as a conductive layer of about 10 9 -10 ohm-cm or less. Therefore, there is a large degree of freedom in this conductive layer formation method, and (a) gold, silver, copper,
There are two methods: vapor deposition of metals such as tin, lead, lead/tin, indium, etc., and (b) electroless plating of the above metals such as gold, silver, copper, etc.
第２の工程は半導体装置組立工程であり、上記
電導層形成工程において製作された、すべての外
部リードが短絡された半導体装置用パツケージに
半導体素子を塔載し封入する工程である。この工
程においては、ワイヤ・ボンデイングがなされる
ので、静電破壊の危険に加えて、他の電気的な原
因による破壊の危険もあるが、パツケージのすべ
ての外部リードが電導層によつて短絡されている
から、塔載される半導体素子が危険にさらされる
ことは皆無で、保護効果は完全である。 The second step is a semiconductor device assembly step, in which the semiconductor element is mounted and encapsulated in the semiconductor device package manufactured in the conductive layer forming step, in which all external leads are short-circuited. In this process, wire bonding is performed, so all external leads of the package are shorted by the conductive layer, which in addition to the risk of electrostatic discharge damage also poses a risk of damage from other electrical sources. Therefore, the mounted semiconductor devices are never exposed to any danger, and the protection effect is complete.
本発明に係る、半導体装置の保護方法の保護機
能が発揮されるのは、この状態においてであり、
この状態において、運搬・保管され、更には製品
として販売されることができる。 It is in this state that the protection function of the semiconductor device protection method according to the present invention is exhibited,
In this state, it can be transported, stored, and even sold as a product.
第３の工程は電導層除去工程であり、試験又は
実装の直前に、上記の電導層を除去する工程であ
る。この工程は、パツケージの電導層部分を半田
浴中に浸漬するだけで容易に実現できる。そし
て、半導体装置は実装にあたつて、その外部リー
ドをはんだメツキする予備はんだ工程を加えられ
ることが一般であるから、この場合は、この電導
層除去工程は何ら附加的工程とはならない。 The third step is a conductive layer removal step, in which the conductive layer is removed immediately before testing or packaging. This process can be easily accomplished by simply immersing the conductive layer portion of the package in a solder bath. When semiconductor devices are mounted, a preliminary soldering process for soldering the external leads is generally added, so in this case, this conductive layer removal process is not an additional process.
以下に本発明の一実施例を示す。 An example of the present invention is shown below.
本実施例にあつては、外部リードが半導体装置
用パツケージの表面で終端しているいわゆるリー
ドレス型半導体装置に、本発明を適した例を示
す。 In this embodiment, an example in which the present invention is applied to a so-called leadless semiconductor device in which external leads are terminated on the surface of a package for a semiconductor device will be shown.
第１図は、セラミツク材から構成される半導体
装置用パツケージ基体１１に、内部配設パターン
１２及び該内部配線パターン１２に連続し該パツ
キージ基体１１の外表面に導出延在された外部リ
ード１３が配設された状態を示す。ここで１４は
半導体素子収容孔である。かかる構造は、セラミ
ツクグリーンシート及びモリブデン―マンガンメ
タライズ法を用いる周知の多層セラミツク板製造
技術により構成される。 FIG. 1 shows a semiconductor device package base 11 made of a ceramic material, and an internal arrangement pattern 12 and an external lead 13 extending from the internal wiring pattern 12 to the outer surface of the package base 11. Indicates the installed state. Here, 14 is a semiconductor element housing hole. Such a structure is constructed using well-known multilayer ceramic board manufacturing techniques using ceramic green sheets and molybdenum-manganese metallization.
ここで、パツケージ基体１１は、直方体であつ
て、外部リード１３はパツケージ基体１１の下面
にあつて各辺の縁部に複数個配設される。 Here, the package base 11 is a rectangular parallelepiped, and a plurality of external leads 13 are disposed on the lower surface of the package base 11 at the edges of each side.
本発明によれば、次の工程において、かかる構
造を有するパツケージ基体１１の下面に金
（Au）を蒸着し、第２図に示されるように、各外
部リード１３間を電気的に短絡する導電層１５を
形成する。該導電層１５は厚さが100〔オングス
トローム〕であれば十分である。 According to the present invention, in the next step, gold (Au) is vapor-deposited on the lower surface of the package base 11 having such a structure, and as shown in FIG. Form layer 15. It is sufficient that the conductive layer 15 has a thickness of 100 angstroms.
しかる後、第３図に示されるように、パツケー
ジ本体１１の半導体素子収容部に半導体素子１６
を収容固着し、該半導体素子の電極と内部配線パ
ターン１２とをリード線１７によつて接続する。
そして該半導体素子１６を覆つてセラミツクある
いは金属から構成される蓋（キヤツプ）１８を固
着し、半導体素子１６を気密封止する。 Thereafter, as shown in FIG.
The electrodes of the semiconductor element and the internal wiring pattern 12 are connected by lead wires 17.
A cap 18 made of ceramic or metal is then fixed to cover the semiconductor element 16, thereby hermetically sealing the semiconductor element 16.
このようにして構成された半導体装置にあつて
は、この後、静電気をおびた物体に接触しても、
全ての外部リードが同一レベルとなるため、半導
体素子の破壊は防止される。 With the semiconductor device configured in this way, even if it comes into contact with an object charged with static electricity,
Since all external leads are at the same level, damage to the semiconductor element is prevented.
なお前述の如き組立て工程を終了した後に行な
われる試験段階にあつては、前記外部リード１３
が電気的に独立している必要がある。したがつ
て、かかる試験に先立つて前記導電層１５を除去
する必要がある。この導電層１５の除去は、外部
リード１３への予備半田処理と兼ねることができ
る。すなわち、パツケージ基体１１を半田浴に接
触させ外部リード１３の表面に半田被覆層を形成
する際、金は半田浴中へ拡散し除去される。 In addition, in the test stage performed after completing the assembly process as described above, the external lead 13
must be electrically independent. Therefore, it is necessary to remove the conductive layer 15 prior to such testing. This removal of the conductive layer 15 can also serve as a preliminary soldering process to the external leads 13. That is, when the package base 11 is brought into contact with a solder bath to form a solder coating layer on the surface of the external leads 13, gold is diffused into the solder bath and removed.
なお、前記試験後、半導体装置の移送等の際
に、該半導体装置が静電気によつて破壊されるこ
とを防止するために、該半導体装置に再び導電層
の被覆を行つてもよい。 After the test, the semiconductor device may be covered with a conductive layer again in order to prevent the semiconductor device from being destroyed by static electricity during transport or the like.
以上説明せるとおり、この方法においては、半
導体装置用パツケージのすべての外部リードが短
絡された状態で半導体素子の組み込みがなされ、
その後も、試験又は実装の直前までの期間、運
搬・保管の期間も含めて、半導体装置のすべての
外部リードは完全に短絡されているから、静電破
壊やその他の電気的原因より、半導体素子が破壊
される危険は皆無であり、完全な保護効果が発揮
される。しかも、この外部リードの短絡はパツケ
ージ外表面の電導層を形成することによつてなさ
れるので、簡易であり、更に、保護を必要としな
くなつたとき、すなわち、試験又は実装にあたつ
て、この電導層が極めて簡易に除去しうるので、
この保護効果をうるに要する副次的不利益も殆ん
どない。又、第１，第２，第３の各工程は、これ
を同時に実施する必要はなく、むしろ、各工程
が、夫々時及び場所を異にして実施されるべき性
質を有する。したがつて、第１の工程又は第２の
工程を加えられた物、特に第２の工程終了後の物
が製品として販売されることができる。この場合
も、この製品の購入者が第３の工程を実施するこ
とにより、この方法の効果が完成することは勿論
である。 As explained above, in this method, the semiconductor element is assembled with all the external leads of the semiconductor device package short-circuited,
Even after that, all external leads of the semiconductor device are completely short-circuited during the period immediately before testing or mounting, including the period of transportation and storage, so the semiconductor device is protected from electrostatic damage and other electrical causes. There is no risk of destruction and full protection is achieved. Moreover, this short-circuiting of the external leads is done by forming a conductive layer on the outer surface of the package, so it is easy to short-circuit, and when protection is no longer required, that is, during testing or mounting. Since this conductive layer can be removed extremely easily,
There are also few side effects required to obtain this protective effect. Furthermore, the first, second, and third steps do not need to be performed simultaneously; rather, each step has the property of being performed at different times and locations. Therefore, products to which the first step or the second step has been added, particularly products after the second step, can be sold as products. In this case as well, it goes without saying that the effect of this method is completed when the purchaser of this product carries out the third step.
以上説明せるとおり、本発明によれば、簡易で
あり、かつ、附加的工程を殆んど要することな
く、しかも、十分な保護効果を発揮する、半導体
装置の保護方法を提供することができる。 As described above, according to the present invention, it is possible to provide a method for protecting a semiconductor device that is simple, requires almost no additional steps, and exhibits a sufficient protection effect.
第１図乃至第３図は、本発明にかかる半導体装
置の製造方法を示す断面図である。
図において、１１……パツケージ基体、１３…
…外部リード、１５……導電層、１６……半導体
素子。
1 to 3 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention. In the figure, 11...package base, 13...
...External lead, 15...Conductive layer, 16...Semiconductor element.
Claims (1)
の外表面に、前記外部リードをすべて短絡させる
ため、蒸着あるいは無電解メツキにより電導層を
形成し、前記半導体装置用パツケージに半導体素
子を搭載し封入する組立工程および運搬等が終了
した後、前記電導層を半田浴に浸漬することによ
り除去して前記外部リードの短絡状態を解除する
ことを特徴とする半導体装置の保護方法。 ２ 前記半導体装置用パツケージはリードレスパ
ツケージであることを特徴とする特許請求の範囲
第１項記載の半導体装置の保護方法。[Claims] 1. A conductive layer is formed on the outer surface of a semiconductor device package having external leads by vapor deposition or electroless plating in order to short-circuit all the external leads, and a semiconductor element is mounted on the semiconductor device package. A method for protecting a semiconductor device, which comprises removing the conductive layer by immersing it in a solder bath to release the short-circuited state of the external leads after the assembly process of mounting and enclosing, transportation, etc. are completed. 2. The method for protecting a semiconductor device according to claim 1, wherein the semiconductor device package is a leadless package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17098479A JPS5694764A (en) | 1979-12-28 | 1979-12-28 | Protection method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17098479A JPS5694764A (en) | 1979-12-28 | 1979-12-28 | Protection method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5694764A JPS5694764A (en) | 1981-07-31 |
| JPS6250980B2 true JPS6250980B2 (en) | 1987-10-28 |
Family
ID=15914967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17098479A Granted JPS5694764A (en) | 1979-12-28 | 1979-12-28 | Protection method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5694764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0642213U (en) * | 1992-11-11 | 1994-06-03 | 大日本インキ化学工業株式会社 | Delivery slip |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629920B2 (en) * | 1982-11-04 | 1994-04-20 | セイコーエプソン株式会社 | Method for manufacturing liquid crystal electro-optical device |
| JPS6177345A (en) * | 1984-09-21 | 1986-04-19 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| DE102004064150B4 (en) * | 2004-06-29 | 2010-04-29 | Osram Opto Semiconductors Gmbh | Electronic component with housing with conductive coating for ESD protection |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS576255A (en) * | 1980-06-12 | 1982-01-13 | Kikai Syst Shinko Kyokai | Solar heat collector |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50105545U (en) * | 1974-02-04 | 1975-08-30 |
-
1979
- 1979-12-28 JP JP17098479A patent/JPS5694764A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS576255A (en) * | 1980-06-12 | 1982-01-13 | Kikai Syst Shinko Kyokai | Solar heat collector |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0642213U (en) * | 1992-11-11 | 1994-06-03 | 大日本インキ化学工業株式会社 | Delivery slip |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5694764A (en) | 1981-07-31 |
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