JPS6248390B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices such as diodes and transistors using amorphous semiconductors.

Traditionally, semiconductor devices have been manufactured using as perfectly crystalline materials as possible. This is because if the material is not a crystalline material, the movement of electrons will be poor (that is, the mobility will be low), and it will not be possible to obtain P-type or N-type semiconductors. The reason for this is that in crystalline semiconductors, the conduction band, forbidden band, and valence band are clearly separated, but in amorphous semiconductors,
The separation of these bands is unclear, and there are many localized electron levels in the forbidden band, 〓10 ¹⁹ cm ^-3 .
This is because electrons are distributed in these localized levels and cannot exist in the conduction band. Therefore, electrons cannot move freely, resulting in a material with very low mobility. Furthermore, even if donors and acceptors are doped to create P-type and N-type materials, the extra electrons and holes will fall into a large number of localized levels in the forbidden band, causing the overall As a result, the effect became negligible, and it was impossible to raise or lower the Fermi level. Such localized levels in the forbidden band are thought to be formed by defects that inevitably occur during amorphous amorphous formation and non-uniformity of bond lengths and angles between atoms (long-range disorder). .

However, as seen in JP-A-52-16990, there is a known method of decomposing SiH ₄ (silane) gas using glow discharge to produce amorphous silicon. Compared to amorphous silicon produced by conventional methods, there are sufficiently fewer localized levels in the forbidden band, and like crystalline semiconductors, the Fermi level can be easily changed when doped with impurities. I have come to realize that it is possible to do this. In fact, when making amorphous silicon by glow discharge, SiH ₄
For example, when B ₂ H ₆ (diborane) gas is mixed in with the gas, P-type thermoelectromotive force is observed, and PH ₃
When it is made by mixing (phosphine) gas, N-type thermoelectromotive force can be easily observed. In addition, materials have been obtained that allow measurements of the Hall effect. If the amount of impurities mixed in is about 10 ¹⁸ - 10 ¹⁹ cm ^-3 , the resistivity will decrease by 9 to 10 orders of magnitude compared to the case where nothing is added, and ρ≒0.01 to 10 Ω cm at room temperature. I became able to do things. However, in the case of a crystal, when the same amount of impurities is added, ρ≒0.001 to 0.01 Ω·cm at room temperature, so the resistivity of amorphous amorphous does not fall as low as that of a crystal. This is also due to the essential properties of amorphous semiconductors.

In amorphous semiconductors, films are formed at temperatures below 500°C to avoid crystallization into polycrystals, so sufficient thermal energy cannot be obtained during film formation, and atoms do not rearrange after bonding. Therefore, the arrangement of atoms is much more disordered than in crystals, and even if chemical bonds are completely formed, a band of localized levels will inevitably remain between the conduction band and the forbidden band. If impurities are doped in this state, the Fermi level will be created within this localized level, and electrical conduction will occur by hopping localized levels near the Fermi level, rather than through the conduction band with higher energy. By doing (hopping), conditions become more convenient for conduction. Such conduction is usually called variable range hopping conduction.
conduction), and the mechanism has been explained by Mott et al. Figure 1 shows the actual
This figure shows the temperature change in resistivity of N-type amorphous silicon made by a glow discharge method by mixing PH ₃ gas and SiH ₄ gas. As you can see, it fits Mott's formula ρ=ρ ₀・exp [(T ₀ /T)] ……(1) well up to around room temperature. Variable range hopping conduction occurs in the case of crystalline semiconductors. At high temperatures, electrons are activated in the conduction band where the energy is relatively low, and conduction by carriers that move freely there is large. I can't. However, in the case of amorphous semiconductors, the conduction band is located at a high energy region and the mobility there is small, so the effect of variable range hopping conduction becomes noticeable even at high temperatures. In equation (1) above, lmρ is T ^- 〓
The slope T ₀ 〓 when plotted is expressed as T ₀ =16α ³ /kN(E _F ) (2). Here, α is the amount indicating the attenuation of the wave function at the localized level, and N(E _F ) is the density of state number (cm ^-3・eV ^-1 ) near the Fermi level.
It is assumed that the energy E of |E−E _F |=kT〓T ₀ 〓 is almost constant. k is Boltzmann's constant. The amount α in this equation can be estimated from the data of the X-ray diffraction pattern.

Figure 2 shows the X-ray diffraction pattern of the same sample, and it shows that in amorphous silicon,
It can be seen that the atomic arrangement is equivalent to the crystal state over approximately 50 Å. This means that within the 50 Å region, the wave functions of each localized level are in the same phase, and even though they are localized, electrons are allowed to exist with almost equal probability in the 50 Å region. In other words, it can be considered as 1/α〓50Å...(3). This is an order of magnitude smaller value of α than, for example, in the case of amorphous silicon made by vapor deposition (α˜1/6 Å ⁻¹ ). Therefore, it can be seen that the gradient T ₀ is small, and in equation (1), a sufficiently small resistivity can be obtained even at room temperature by this variable range hopping conduction. The value of N(E _F ) shown in FIG. 1 is calculated from the value of α and its slope. Also, FIGS. 3A and 3B show P
This is an imaginary drawing of the state density of these samples doped with . B using B ₂ H ₆ gas
When doped with , P-type amorphous silicon is produced. The conduction mechanism also shows the conduction characteristics of variable range hopping.

The present invention provides a variable range as described above.
It was invented by applying the conduction characteristics of hopping to a PIN amorphous semiconductor device. (e.g., a P-type amorphous silicon layer and an N-type amorphous silicon layer), and a high resistivity region (e.g., an intrinsic amorphous silicon layer) interposed between these first and second regions and made of an amorphous semiconductor.
In the semiconductor device, at least the first region is configured to have variable range hopping conduction characteristics. According to the present invention configured as described above, it is possible to make the resistivity of the low resistivity region three orders of magnitude smaller than that of the corresponding amorphous layer of the aforementioned Japanese Patent Application Laid-Open No. 52-16990. Therefore, the low resistivity region (that is, the amorphous layer) itself can be used as an electrode having ohmic properties like a metal. Therefore, when manufacturing a semiconductor device, electrodes can be formed continuously without performing a metal electrode forming process different from the semiconductor forming process. Further, even if an amorphous semiconductor is used, the resistivity of the low resistivity region can be made extremely low, so that the electrical characteristics of the semiconductor device can be improved. In particular, when the present invention is applied to solar cells, the series resistance of the semiconductor layer can be reduced, so the saturation current can be increased.
As a result, photoelectric conversion efficiency can be greatly improved.

According to the present invention, when P-type and N-type amorphous materials are directly bonded, as shown in FIG. 4A,
Since there is a very large density of states near the Fermi level, the carrier moves freely by hopping between junctions, making it impossible to obtain rectifying characteristics. Therefore, in order to obtain diode characteristics, an undoped I layer (intrinsic layer) must be inserted between the P layer and the N layer, as shown in FIG. 4B. This I
The layer corresponds to a depletion layer when made of a crystalline material. In such a case, if an external bias is applied, an electric field will be applied to the I layer as shown in Figure 5A, and in the forward direction, electrons that have flown by variable range hopping will directly enter the conduction band in the I layer. It tunnels or runs through the conduction band via localized levels at the band tails (ends), or it reaches the P layer only via localized levels in the I layer. On the other hand, when the bias is applied in the opposite direction, as shown in FIG. 5B, both electrons and holes move away from the interface of the I layer, and no current flows. If the reverse bias voltage is increased further, a breakdown phenomenon will occur using the same mechanism as a normal diode. Therefore, such P-I-
The diode characteristics of the N amorphous layer are as shown in FIG.

Even if the I layer is made of the same amorphous material, if the density of states in the forbidden band is large, no electric field will be applied from the beginning, so the density of states in the forbidden band must be minimized. Must be. Such amorphous can be made by, for example, mixing a small amount of H (hydrogen). In other words, in undoped amorphous silicon made using the high-frequency glow discharge method, this hydrogen eliminates dangling bonds and significantly reduces the number of localized levels due to defects in the forbidden band. ing. Note that similar characteristics may be obtained even if a high resistivity layer such as an N ^- layer or a P ^- layer is used instead of the I layer. In addition, carrier injection into the I layer may be facilitated by providing a somewhat distributed space charge in the thickness direction of the I layer, rather than being uniform over its entire thickness.

The feature of the present invention is that, unlike a PN junction diode made of a crystalline material, between the P and N layer interfaces,
An amorphous layer with a very low density of states (less than 10 ¹⁶ ) is arranged, and the charge transport to this interface is
It uses the mechanism of variable range hopping. This is possible because even amorphous silicon has a crystal-like atomic arrangement structure in a considerable region (~50 Å), and it also has impurities at ~10 ²⁰ cm.
The point is that he was able to dope up to ^-3 . In this variable range hopping conduction, as already mentioned in Fig. 1, the logarithm of the resistivity ρ is approximately proportional to the -1/4th power of the absolute temperature T〓 (ρ∝T ^- 〓) This is because the doped impurity concentration is high, and carrier hopping occurs within the localized level due to the impurity. In this case, the above proportional relationship is -150℃
(123〓) or more, especially in the practical temperature range, i.e. 300~400
It is known that this holds true at 〓 (27 to 177℃). In addition, a high resistivity region such as the I layer sandwiched between the low resistivity P and N layers is essential to obtain rectifying properties, but if the thickness is too thin, tunneling will occur and the rectifying properties will be impaired. Because it becomes scarce,
The thickness is preferably 50 Å or more.

On the other hand, the above-mentioned Japanese Patent Application Laid-Open No. 16990/1983 discloses forming a P ⁺ -N ⁺ structure using amorphous silicon by a glow discharge method, but this has rectifying properties. There is no mention of anything that is not done. If a variable hopping conduction mechanism exists as in the present invention, a P-N structure inevitably does not have rectifying properties, as explained in FIG. 4A, but on the other hand, rectifying The appearance of conductivity probably means that conductivity is obtained through another mechanism. That is, Tokukai Sho
In No. 52-16990, hopping in levels due to impurities does not seem to occur, and therefore, although the present invention can obtain a low specific resistance of about 0.01 Ω·cm, the ratio is only about 50 Ω·cm at most. Only low resistance can be obtained.

Next, a method for manufacturing a semiconductor device, such as a diode, according to the present invention will be explained with reference to FIG.

This manufacturing method is a so-called glow discharge method, and the reaction tube 1 is made of quartz, and the RF coil 2 is wound around it. From this, RF oscillator 3
When a high frequency current of 13.56MHz is applied, SiH ₄ and PH ₃
(or B ₂ H ₆ ) decomposes into ions or radicals.
Si, P, H, etc. 4 are generated and adhered to the substrate 5.
The degree of vacuum measured with vacuum gauge 6 at this time was 10 ^-1 ~
10 ^-3 Torr.

The difference between this glow discharge method and amorphous silicon produced by conventional vapor deposition or sputtering methods is that radical atoms or ions 4 approach near the substrate 5, and these have higher energy than RF. , during the formation of an amorphous film, the bonding is complete and a tetrahedral three-dimensional structure is formed over a considerable area. However, the essential difference from crystal formation is that this film formation is not performed in a thermal equilibrium state. In other words, atoms that have finished chemical bonding are rapidly cooled and do not move any further, so atoms are not fixed in the lowest energy state and form crystal grains like in crystals.
Therefore, in the case of crystals, it has never happened that chemical bonds break at the places (grains) where crystal clusters that have started to grow with various orientations collide. Furthermore, in the case of thin films made by vapor deposition or sputtering, it is common for some atoms to stick together and form clusters while they reach the substrate, but these have almost no energy. However, the substrate is rapidly cooled without completing the bonding process. Therefore, amorphous amorphous made by vapor deposition method etc. creates many cavities in the film, and ~10 ²⁰ in the forbidden zone.
This allows a density of states near cm ^-3 . This reduces the influence of doping and is the reason why P- or N-type amorphous amorphous amorphous is not formed. Another advantage of this glow discharge method is that when SiH ₄ is decomposed, H can be introduced into the film, and if this amount is appropriate, the density of states in the forbidden band can be reduced. This is thought to be due to the function of appropriately adjusting the angle and length of chemical bonds to prevent the formation of dangling bonds when forming a three-dimensional tetrahedral structure. Therefore, with this method, it is possible to use amorphous silicon having a particularly low state density for the above-mentioned I layer.

When a diode is manufactured using such a glow discharge method, it has the following advantages from a technical standpoint.

(1) Because amorphous amorphous adheres at low temperatures (300 to 500°C), thin films can be created on inexpensive substrates such as glass and metal.

(2) Because it is deposited at low temperatures, unlike diffusion techniques in crystalline materials, it is possible to create bonds that have very rapid changes when making them.

(3) Since it is a technology that involves stacking thin films, it is in principle possible to create elements with a multilayer structure, that is, a group of elements arranged in three dimensions.

(4) Even with the same amorphous silicon, the range of resistivity can be changed from ρ = 10 ¹¹ Ω・cm to ρ = 0.01 Ω・cm 13 depending on the amount of doping, the temperature during manufacturing, and the magnitude of RF power. It is therefore possible to continue to make insulating layers and wiring leads from the same amorphous silicon.

It is predicted from the many features mentioned above that by making diodes with good characteristics using amorphous silicon materials, it will be possible to efficiently create new devices that are not available with conventional crystalline materials.

Amorphous Si produced by such glow discharge method
What is doped with P or B is a hopping conduction between impurity levels, that is, a variable range hopping conduction that occurs near the Fermi level in this case.
You can get an idea from Figure 1. The amount of dopant gas in this case is, for example, in the case of PH ₃ , PH ₃ /SiH ₄ = 3.2×
It ranges from 10 ^-5 to 2.5×10 ^-3 . However, in amorphous Si containing a smaller number of impurities,
As shown in Figure 8, data indicating active type conduction (i.e., caused by electrons flying to the extended state above the impurity level, rather than due to the above-mentioned hopping) was obtained. ing.

Next, FIG. 9 shows an example of a junction diode made by combining low resistivity amorphous materials. In this case, first, on the glass substrate 5 at 300°C,
When several micrometers of amorphous amorphous is deposited by glow discharge using a mixed gas of approximately PH ₃ /SiH ₄ = ~10 ^-3 , a low-resistance layer 7 with a specific resistance ρ = 0.01 Ωcm at room temperature is formed.
I can do it. Next, the substrate temperature is lowered, the RF power is also reduced, and an I layer 8 having a thickness of about 0.5 μm is formed.
This layer contains several to several tens of at% of H atoms, and the density of states in the forbidden band is extremely small. When attaching the I layer 8, a suitable mask is applied so that the N layer 7 is not completely covered. Then apply another mask,
For example, B ₂ H ₆ /SiH ₄ =~10 ^-3 on the I layer 8
A doped P-type layer 9 is applied. Finally, N-type layer 7
By attaching an electrode to the P-type layer 9, a desired diode can be obtained. This characteristic is shown in FIG. No matter what metal (e.g. Au) is used as the electrode,
Since the amorphous layers 7 and 9 have a Fermi level in the impurity level and exhibit metallic properties, ohmic contact can always be established. FIG. 10 shows an example in which two diodes are connected in series on the same substrate 5. In this example, an N-type layer 10 is placed on a P-type layer 9, and an I-layer 8 is placed on a P-type layer 11 on the other hand.
An N-type layer 12 is formed through the . In this diagram, I
It should be noted that a PN junction without intervening layers is not a diode, but merely serves as an ohmic connection. FIG. 11 shows an example in which the same structure as that shown in FIG. 10 is made on a metal substrate 15, and the process is simple and the device has a simple structure.

In the examples shown in FIGS. 9 to 11, for example, before forming each semiconductor region 7, a high resistivity layer, for example, another intrinsic amorphous Si layer not doped with impurities, is previously formed on the surface of the substrate 5 by glow discharge. The semiconductor region 7 can also be formed on this amorphous Si layer by phase growth. In this case, due to the presence of the above-mentioned high resistivity layer, atoms from the substrate are mixed into the above-mentioned low resistivity layer 7 by sputtering during discharge (that is, the substrate 5 into the low resistivity amorphous layer 7).
effect) is prevented. Therefore, since the above-mentioned high resistivity layer acts as a so-called buffer layer, the RF electric field when creating the low resistivity layer has an ideal distribution, and even if the amount of impurity supply gas is small, it can produce a low resistance, e.g. A semiconductor region 7 of <0.01 Ω·cm can be obtained easily and accurately. This high resistivity layer may be made of intrinsic amorphous silicon without doping with impurities, and may be formed using the same equipment used to vapor phase grow the low resistivity amorphous semiconductor layer described above. desirable. In this case, it is preferable to vapor phase grow the intrinsic amorphous silicon layer (buffer layer) while applying discharge energy lower than the discharge energy used when forming the low resistivity amorphous semiconductor layer. For example, it is desirable to form the buffer layer with an RF power that is 1/3 to 1/2 of the RF power used when forming a low resistivity amorphous semiconductor layer.

This buffer layer may be composed of a high resistivity amorphous layer having a resistivity of 10 ⁶ Ω·cm or more and/or an intrinsic amorphous layer not doped with impurities. That is, if the resistivity is less than 10 ⁶ Ω·cm, the buffering effect will be poor and the insulation effect when the element is manufactured will also be weak. In order to perform these functions well, it is desirable that the specific resistance of the buffer layer is 10 ⁹ to ^{10 12} Ω·cm or more.
There is also a desirable range for the thickness of this buffer layer, which is 200 Å considering the buffer action and insulation properties.
The above is desirable. The structure of the buffer layer can also be modified depending on the purpose. For example, by first forming an amorphous layer with a resistivity of 10 ⁶ Ω・cm or more on the substrate surface, and then forming an intrinsic amorphous layer, the structure of the buffer layer can be modified depending on the purpose. It is also possible to have a double structure.

During glow discharge when doping impurities, the resistivity changes depending on the RF power, and the RF
It has been found that the resistivity is minimized when the power is appropriate, and that the doping effect is comparable to that obtained with crystalline silicon. That is, it is thought that when the RF power is small, the decomposition of PH ₃ is insufficient, the decomposed P does not enter the position of the Si atom, or the tetrahedral structure is no longer formed. on the other hand,
This is thought to be due to the fact that in areas where the RF power is high, the substrate may be sputtered or the bonds in the formed film may be cut by themselves.

In this embodiment, before forming the impurity-doped amorphous silicon layer 7, an undoped intrinsic amorphous silicon layer is first applied on the substrate 5, and then the doped layer 7 is applied. By doing this, compared to the case where the doped layer is directly attached to the substrate,
Even with the same amount of doping gas, a doped layer with low resistivity can be formed. This is because P atoms (or B atoms) replace Si atoms and become easier to enter the amorphous amorphous, or when Si atoms adhere to the substrate due to glow discharge, the substrate is sputtered and O atoms etc. are mixed in. It may be possible to prevent this from happening. Furthermore, in the early stage of film formation, the strength of the RF electric field may vary depending on the type of substrate even under the same conditions.

Note that the substrate 5 may be made of not only quartz glass but also other insulators or metals, but when making an amorphous silicon device, first
Attach approximately 0.5 to 1.0μ of amorphous silicon (10 ⁶ Ω・cm). That is, after applying the undoped layer, N
Add mold layer 7, etc. In this case, a buffer layer to eliminate the influence of the substrate on the amorphous layer,
That is, the conditions for forming the undoped layer are preferably such that the RF power is reduced by adding H without adding impurities. For example, the substrate temperature
300℃, SiH ₄ pressure 4×10 ^-2 TorrRF power 40~60
(on an arbitrary scale), good results were obtained. When the optical absorption coefficient α of the undoped amorphous Si layer produced in this manner was examined, it was found that it well satisfies the relationship √=A(hν−Eg), which is a characteristic of an amorphous semiconductor. In this case, Eg (optical energy gap) = 1.8 eV. Such a large optical energy gap indicates that this type of amorphous semiconductor has few localized levels in the forbidden band and is of good quality. Further, the specific resistance in this case is ρ≧10 ¹⁰ Ω·cm. The specific resistance of the low-resistance amorphous layer thus formed on the undoped layer can be as small as 0.1Ω・cm or less even when using a mixed gas of PH ₃ /SiH ₄ = 2.5×10 ^-5 , for example. .

Although the present invention has been described above with reference to embodiments, this embodiment can be further modified based on the technical idea of the present invention. For example, amorphous semiconductors other than amorphous silicon can be used, and P-type layers and N
Either one of the mold layers may be composed of an amorphous material according to the invention. Further, the above-mentioned buffer layer can also be formed by a method other than the glow discharge method. Of course, the present invention can also be applied to devices other than diodes, such as transistors.

[Brief explanation of the drawing]

The drawings are for explaining the present invention, and
Figure 1 is a comparison diagram showing temperature changes in specific resistance of amorphous silicon doped with impurities, Figure 2 is an X-ray diffraction diagram of the amorphous silicon, and Figures 3A and 3B are the states of the amorphous silicon. A graph showing the density, Figure 4A is an energy band diagram of a PN junction made of the same amorphous silicon,
Figure 4B is an energy band diagram of a PIN junction diode with an intrinsic amorphous silicon layer that is not doped with impurities, and Figure 5A is the energy band diagram of a PIN junction diode when this PIN diode is forward biased. The band diagram, Figure 5B is the energy band diagram when the same diode is biased in the reverse direction, Figure 6 is the IV characteristic diagram of the same diode, and Figure 7
The figure is a schematic cross-sectional view of the equipment used in the glow discharge method.
Figure 8 is a graph showing the conductivity of amorphous silicon with a small amount of impurities, and Figure 9 is a graph showing the conductivity of amorphous silicon with a small amount of impurities.
A vertical cross-sectional view of an example of a junction diode, Fig. 10 is a vertical cross-sectional view of an example in which two of the above PIN junction diodes are connected in series, and Fig. 11 is a longitudinal cross-sectional view of an example similar to Fig. 10 using a metal substrate. It is a front view. In addition, in the symbols used in the drawings, 2...
...RF coil, 4...Ion or radical, 5...
...Substrate, 7,12...N-type amorphous silicon layer, 8...Intrinsic amorphous silicon layer, 9,1
1...P-type amorphous silicon layer, 15...metal substrate.

Claims (1)

[Claims] 1. First and second regions of low resistivity that are of different conductivity types and made of amorphous semiconductors, and interposed between these first and second regions and made of amorphous semiconductors. What is claimed is: 1. A semiconductor device comprising high resistivity regions, wherein at least the first region is configured to have variable range hopping conduction characteristics.