JPS6245576B2 - - Google Patents

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a system in which a lower device having a data buffer memory receives data transferred in bytes from a higher device to the data buffer memory, and particularly relates to a method for data transfer. It relates to a data transfer method that performs at high speed.

(b) Prior Art and Problems When a lower-level device, such as an input/output device, having a data buffer memory receives data transfer from a higher-level device, such as a multiplexer channel, it sets a data request bit and requests the higher-level device to transfer data. The host device checks the bits of the data request and transfers the data one byte at a time, but each time it transfers one byte, it checks whether the transfer is complete. This data transfer method is called a byte multiplex mode, but it has the disadvantage that the data transfer speed is slow because it checks for completion of transfer every time one byte is transferred.

(c) Purpose of the invention The purpose of the present invention is to eliminate the above-mentioned drawbacks,
Byte-by-byte data transfer is performed using N×M byte local bursts that transfer N×M bytes at once.
The remaining storage area of data buffer memory is N×M
-When the data becomes less than 1 byte, the data is transferred 1 byte at a time, and the data transfer is terminated when the recording of the data buffer memory is completed, thereby improving the data transfer speed and, by extension, the efficiency of the system. .

(d) Structure of the Invention The structure of the present invention is as follows: M registers of N bytes, two counters of L bits, and one status register of the lower device.
Data transfer is performed in N×M byte local bursts, and when it is detected that the remaining storage capacity of the data buffer memory is less than N×M-1 bytes, the data transfer is switched to 1-byte byte data transfer. Data transfer is terminated upon completion of recording in the data buffer memory.

(e) Embodiment of the Invention The figure is a block diagram of a circuit showing an embodiment of the invention, in which N is 4, M is 1, and L is 2. When receiving data transfer from the higher-level device 11, the control section 10 sets the DRQ bit of the status register 1 of the lower-level device to "1" to request data transfer. Upper device 1
1 means that when the DRQ bit of the status register 1 of the lower device becomes "1" and it becomes aware of a data transfer request, it checks the LAST bit of the status register 1 of the lower device, and if it is "0", the data to be transferred is When the number of bytes is 4 or more, 4 bytes are sent to the 4-byte register 7, and when it is less than that, that many bytes of data are sent to the 4-byte register 7. The number of transferred bytes is set in a 2-bit write address counter 2. The data entered in the 4-byte register 7 is sequentially written byte by byte into the data buffer memory 5 by the multiplexer 6, and the control section 10 counts the number of bytes of this data and sets it in the 2-bit read address counter 3. When the matching circuit 4 reports to the control unit 10 that the values of the write address counter 2 and the continuous address counter 3 match, the control unit 10 completes writing of the data in the 4-byte register 7 to the data buffer memory 5. It then sets the DRQ bit in the status register 1 of the lower device to "1" again and requests the higher device 11 to transfer the next data. If the data to be transferred by the host device 11 is 4 bytes or more, the above operation is repeated, and if the data is 3 bytes or less, the data transfer ends.

When the control unit 10 detects that the remaining storage area of the data buffer memory 5 is 3 bytes or less from the count value of the byte counter 9 while repeating the above operation, it sets the flip-flop 8 and changes the status register 1 of the lower device. Set the LAST bit to “1”.
When the host device 11 detects that the LAST bit becomes "1", it switches data transfer every 4 bytes to data transfer every 1 byte. When the storage area of the data buffer memory 5 becomes full and recording is completed, the byte counter 9 becomes "0", resets the flip-flop 8, and reads the status register 1 of the lower device.
Set the LAST bit to “0”. The host device 11
When the LAST bit changes from "1" to "0", data transfer completion is detected and the data transfer is terminated.

(f) Effects of the Invention As explained above, the present invention has N×
Transfer speed is improved because data is transferred in M bytes at a time, and when the storage area of the data buffer memory becomes less than N x M - 1 bytes, the transfer is switched to 1 byte at a time so that the transferred data does not overflow. The effect is great because the efficiency of the system can be improved without causing data loss.

[Brief explanation of the drawing]

The figure is a block diagram of a circuit showing one embodiment of the present invention. 1 is the status register of the lower device, 2 and 3 are 2-bit counters, 4 is the match circuit, 5 is the data buffer memory, 6 is the multiplexer, 7 is the byte register, 8 is the flip-flop, 9 is the byte counter, and 10 is the control. 11 is a host device.

Claims (1)

[Claims] 1. In a lower device that has a data buffer memory and receives data transfer from the upper device, M registers of N bytes, two counters of L bits, and one status register of the lower device are provided to facilitate data transfer. When the remaining storage area of the data buffer memory is N×M-1 bytes or less, the data is transferred byte by byte and the data is transferred when the recording of the data buffer memory is completed. A data transfer method characterized by terminating.