JPS6244360B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample and hold circuit, and in particular to a servo control circuit that samples and holds a predetermined error information signal and uses this hold output to control the operation of a circuit, rotating equipment, etc. to a constant state. The present invention relates to a sample and hold circuit suitable for use.

In an information reading device that reads recorded information recorded on a recording medium, a servo circuit for time axis correction is provided to accurately correct the time axis of a reproduced signal. In particular, the servo circuit is indispensable for the reproduction of color video information, but in this case, the phase error signal obtained by comparing the phase of the color burst signal in the reproduction information with the reference phase is 1H (one horizontal scanning section). Samples and holds are performed every approximately 63.5 μs), and the time axis of the reproduced signal is corrected by this hold output.

In such a time base correction circuit, the phase error signal level becomes extremely large due to the dropout of the burst signal due to dropout and the influence of noise in the synchronization signal due to dropout, and this is held in the sample and hold circuit and output. However, since this is incorrect phase information, the time axis correction operation is disturbed. Therefore, color unevenness will occur over several H times in the reproduced image.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sample and hold circuit that can hold and output only proper sampling values and eliminate malfunctions of servo circuits that perform time axis correction and the like.

Another object of the present invention is to provide a sample and hold circuit for use in a time axis correction circuit that is not adversely affected by dropouts in color burst signals having time axis information.

The sample and hold circuit according to the present invention prohibits sampling operation when the difference between a certain sampling value of an input signal and a value to be sampled subsequently falls outside a predetermined range, and outputs the previous sampling value while holding it. It is characterized by the fact that it is made to do so.

The present invention will be explained below using the drawings.

FIG. 1 is a circuit block diagram of an embodiment of the present invention, in which an input signal to be sampled, for example, a phase error signal for time axis correction of the color video signal mentioned above, is input to a first sample and hold circuit 1. be done. This circuit 1 includes a sample switch _S1 that is controlled on and off by a sampling pulse B,
It consists of a hold capacitor _C1 and a buffer amplifier _A1 . This hold output c becomes each input of the second and third sample and hold circuits 2 and 3. Each of these circuits 2 and 3 includes a switch S ₂ ,
S ₃ , capacitors C ₂ , C ₃ and buffer amplifier A ₂ ,
Consists of A ₃ . The output L of the third sample and hold circuit 3 is used as a sample and hold output which is the overall circuit output, and the output E of the second sample and hold circuit 2 is input to the difference detector 4 and the first
The difference between the output c of the sample and hold circuit 1 and the output c of the sample hold circuit 1 is detected. This difference output is compared with the upper and lower reference levels in the window comparator 5, and the difference detector 4
If the output is outside this reference level range, a low level comparison output F is generated, and if it is within this range, a high level comparison output F is generated. Incidentally, the upper and lower reference levels of this window comparator 5 can be set as desired by a variable resistor VR.

The comparison output F of the comparator 5 serves as one input of an AND gate 6 provided to inhibit the sampling operation of the third sample and hold circuit 3. The output pulse of a delay device 7 that delays the sampling pulse B by about 5 μs is used as another input, and in principle, this delayed output pulse becomes the sampling pulse K of the third sample and hold circuit 3. Further, a delay device 8 is provided, and the sampling pulse B is delayed by about 50 μs and used as a sampling pulse for the second sample and hold circuit 2. Therefore, at the time when the sampling pulse K is output, that is, at a time approximately 5 μs after the generation of the sampling pulse B, the previous value of the sampling value output from the sample and hold circuit 1 is held in the sample and hold circuit 2. There will be.

Furthermore, in this example, an AND gate 9 is provided which has two inputs, a burst gate pulse H and a dropout detection pulse G, in order to eliminate the inconvenience when a dropout occurs in a reproduced color burst. The Q output J of the flip-flop 10 is used as a reset input of the flip-flop 10, and the Q output J of the FF 10 is used as another input of the gate 6. Further, as the set input I of the FF 10, the output of the detector 11 which detects the leading edge of the burst pulse is used. Incidentally, the same effect can be obtained by directly inputting the dropout detection pulse G to the reset input of the FF 10.

FIG. 2 shows waveforms of various parts in the circuit block of FIG. 1, where A is a reproduced color video signal and B to L are the waveforms of B to L in FIG. 1, respectively. It is assumed that the sampling pulse B has a period of 1H, and the output of the first sample and hold circuit 1 sampled by this pulse B is as shown in c. Therefore, the output of the second sample and hold circuit 2 sampled by the sampling pulse D delayed by about 50 μs by the delay device 8 becomes as shown in E.

Therefore, the first and second sample and hold circuits 1 during a period of approximately 50 μs from the generation of the sampling pulse B at times t ₁ to t ₂ and t ₃ to _{t 4} in the figure.
The difference output between and 2 is significantly larger than in other cases, and falls outside the level range set by the window comparator 5. As a result, the comparator output is at a low level during that time as shown at F, so the AND gate 6 is closed, and sampling for the third sample and hold circuit 3 is output approximately 5 μs after the generation of the sampling pulse B. During this time, the pulse is prevented from passing as shown in K, and the third sample-and-hold circuit 3 outputs the previous sampled value while holding it. Therefore, the output of this circuit has a waveform as shown in L, and when a certain sampling value of the input signal and a value to be sampled subsequently fall outside a certain range, the third sample and hold circuit 3 The sampling operation is prohibited, and the previous sampling value is output while being held.

Furthermore, if a dropout occurs at time _t5 during a burst, a dropout detection pulse is generated as shown in G, so the AND gate 9
The output of FF10 becomes high during that time and resets FF10. Therefore, the Q output transitions to a low level as J, and the passage of the sampling pulse for the third sample and hold circuit 3 is blocked by the gate 6, and the previous sampling value is similarly held and becomes the circuit output. Become. The next burst gate pulse sets FF10 and the Q output goes high, causing gate 6 to return to the open state.

In this way, when an abnormality occurs in the phase error signal and there is a significant difference from the previous sampling value, the output L of the third circuit 3, which is the final sample-and-hold output, samples this abnormal value. The previous normal value is maintained without being held. Furthermore, if a dropout occurs during a burst, the risk of phase error abnormality increases significantly, so in this case, the gate 6 is actively closed by the output of the FF 10 to prevent sampling during the dropout period. After that, when the dropout disappears, FF is released at the leading edge of the burst gate.
10 is set to enable sampling.

Note that when detecting and compensating only an abnormality in the input value of the phase error, the gate 9, FF 10, and leading edge detector 11 are not necessary, but by using them together as shown in the figure, dropout can be reduced. This makes it possible to completely eliminate the effects. If compensation is performed by considering only the effect of dropout during burst, the second sample-and-hold circuit 2, difference detector 4, and window comparator 5 are not necessary.

Furthermore, as another example, the first and second
The sample and hold circuits 1 and 2 are omitted, and only the third sample and hold circuit 3 is provided, and the phase difference signal is directly input to the input of this third sample and hold circuit 3. The detector 4 may detect the difference, and the window comparator 5 may compare the levels. By doing so, the circuit can be further simplified.

As described above, according to the present invention, when the input signal is abnormal, the previous sampling value is held and output without sampling it, so that the time in the color video information reproducing device is reduced. It can be used in an axis correction circuit to obtain extremely good effects, and can also be used as a sample hold circuit in various other servo control circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of the present invention, and FIG. 2 is an operational waveform diagram of each part of the circuit of FIG. Explanation of symbols of main parts, 1 to 3...Sample hold circuit, 4...Difference detector, 5...Window comparator, 6...And gate.

Claims (1)

[Claims] 1. When the difference between a certain sampling value of an input signal and a value to be sampled subsequently falls outside a predetermined range, the sampling operation is prohibited and the sampling value is output while being held. A sample hold circuit characterized by: 2. A first sample and hold means for sampling and holding the input signal using a sampling pulse; and a first sample and hold means for sampling and holding the hold output of the first sample and hold means at a timing delayed by a predetermined time with respect to the sampling pulse. 2 sample and hold means, and the first
a third sample-hold means for sampling and holding the hold output by the sample-hold means; and when the difference between the hold outputs of the first and second sample-hold means falls outside the predetermined range 2. The sample-and-hold circuit according to claim 1, further comprising means for inhibiting the sampling operation of said third sample-and-hold means, and the output of said third sample-and-hold means is used as a circuit output. 3 A sample hold circuit used in a time axis correction circuit for color video information, which performs a sampling operation when the difference between a certain sampling value of a time axis error signal and a value to be sampled subsequently falls outside a predetermined range. A first means of prohibition,
a second prohibition means for prohibiting a sampling operation of the time axis error signal when a dropout occurs within a color burst signal equivalent section of the color video information, and a prohibition operation of the first or second prohibition means; Inside is a sample hold circuit characterized by outputting the previous sampling value while holding it.