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JPS6243175A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6243175A
JPS6243175A JP18250885A JP18250885A JPS6243175A JP S6243175 A JPS6243175 A JP S6243175A JP 18250885 A JP18250885 A JP 18250885A JP 18250885 A JP18250885 A JP 18250885A JP S6243175 A JPS6243175 A JP S6243175A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
manufacturing
barrier metal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18250885A
Other languages
Japanese (ja)
Inventor
Michio Asahina
朝比奈 通雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP18250885A priority Critical patent/JPS6243175A/en
Publication of JPS6243175A publication Critical patent/JPS6243175A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、超高速、高信頼性のVLSIデバイスの製造
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an ultra-high-speed, highly reliable VLSI device.

集積度の増加につれ、ジャンクシランは、浅くコンタク
トサイズは、増々小さくなる。
As the degree of integration increases, junk silane becomes shallower and the contact size becomes smaller and smaller.

〔従来の技術〕[Conventional technology]

第2図に従来のデバイスの一例を示したが、このような
構造では、次にあげるような欠点を有する。
An example of a conventional device is shown in FIG. 2, but such a structure has the following drawbacks.

1)ジャンクシ1ン9がα3μ以下になると、配線AL
系合金15と、アロイスパイクが生じ、ジャンクシ冒ン
リークが生じ易くなる。(特にNchが影響する。) 2)AL−3i配線中の81と、基板S1が反応して、
コンタクト界面にP型(AI、ドープ)Slが固相エピ
タキシャル成長し、コンタクト抵抗が非常に、増大、も
しくは、非オーミツクとなる。
1) When the junction 9 becomes less than α3μ, the wiring AL
With alloy 15, alloy spikes are formed, and leakage is likely to occur. (Nch is particularly affected.) 2) 81 in the AL-3i wiring reacts with the substrate S1,
P-type (Al, doped) Sl is solid-phase epitaxially grown at the contact interface, and the contact resistance increases significantly or becomes non-ohmic.

3)ALとコンタクト部S1の反応により、エレクトロ
マイグレーシ冒ンが起こる。
3) Electromigration occurs due to the reaction between AL and contact portion S1.

本発明は、微細化、高集積化に伴い発生するこのような
欠点を解消し、高信頼性の配線方法を提供するものであ
る。
The present invention eliminates these drawbacks that occur with miniaturization and high integration, and provides a highly reliable wiring method.

〔問題を解決するための手段と目的〕[Means and objectives for solving the problem]

本発明は、従来のAL系合金一層にかわり、バリアメタ
ルと、タングステンCVD膜の2層、もしくは、バリア
メタルと、タングステンCVD膜と、AL系合金又はA
L膜の3層配線により、ジャンクシ冒ンスパイク、固相
エビによるコンタクトの劣化、エレクトロマイグレーシ
璽ン断線を、なくし、高信頼性で、超集積、超高速なデ
バイス形成プロセスを提供するものである。
Instead of the conventional single-layer AL-based alloy, the present invention provides a two-layer structure consisting of a barrier metal and a tungsten CVD film, or a barrier metal, a tungsten CVD film, and an AL-based alloy or an aluminum alloy.
The three-layer wiring of the L film eliminates contact deterioration due to junk spikes, solid-phase corrosion, and electromigration wire breakage, thereby providing a highly reliable, ultra-integrated, and ultra-high-speed device formation process.

〔実施例〕〔Example〕

第1図に本発明半導体装置の製造方法の一例を示す。8
1基板1に、LoCOθ2を形成し、アクティブ領域を
つくった後、ゲート酸化膜3.リンドープポリシリコン
4.チタンシリサイド5より成るポリサイドゲートを形
成する。次に、ホットエレクトロン耐性向上の為のライ
トドープイオン打込み層6を形成し、ポリサイド側面に
、R工Eによりサイドウオール7を形成する。続いて、
ソース、ドレイン部のみに、チタンシリサイド層8を、
形成し、高加速、高ドーズイオン打込によるジャンクシ
ロン9を形成する。
FIG. 1 shows an example of a method for manufacturing a semiconductor device of the present invention. 8
1. After forming LoCOθ2 on the substrate 1 and creating an active region, a gate oxide film 3. Phosphorus doped polysilicon 4. A polycide gate made of titanium silicide 5 is formed. Next, a lightly doped ion implantation layer 6 is formed to improve hot electron resistance, and a sidewall 7 is formed on the side surface of the polycide by an R process. continue,
Titanium silicide layer 8 is applied only to the source and drain parts.
Junxiron 9 is formed by high acceleration, high dose ion implantation.

次に層間絶縁膜10をデボジシ1ンし、コンタクトエッ
チ後、チタンナイトライド膜11.タングステンCVD
膜12.AL膜13の5層膜を全面にデポジションする
Next, the interlayer insulating film 10 is deposited, and after contact etching, the titanium nitride film 11. Tungsten CVD
Membrane 12. A five-layer film of the AL film 13 is deposited over the entire surface.

続いて、該5層膜を、R工Eで同時にエツチングして配
線層を形成する。
Subsequently, the five-layer film is simultaneously etched using R/E to form a wiring layer.

〔発明の効果〕〔Effect of the invention〕

本発明により成るデバイスは、コンタクト部が、チタン
シリサイドと、チタンナイトライド、タングステンCV
Dの積層構造である為、ALと81との反応、Slの固
相エビ、エレクトロマイグレーシラン劣化が殆どなく、
コンタクト抵抗も低く、550℃まで安定に使えること
を確認した。
In the device according to the present invention, the contact portion is made of titanium silicide, titanium nitride, and tungsten CV.
Due to the laminated structure of D, there is almost no reaction between AL and 81, no solid phase of Sl, and no deterioration of electromigration silane.
It was confirmed that the contact resistance was low and that it could be used stably up to 550°C.

実施例においては、チタンポリサイドゲート。In the example, a titanium polycide gate.

ソース、ドレイン部は、チタンシリサイド、バリアメタ
ルとして、チタンナイトライドをあげたが、他のごリサ
イドゲート(例えばモリブデンポリサイド、又は、通常
ポリシリコンのみ)、ソース、ドレインは、他のシリサ
イド(例えばジルコニウムシリサイド)でも勿論可能で
あり、バリアメタルもチタンタングステンでも有効であ
る。要は、バリアメタルと、タングステンCVDの積層
構造により、基本的な、特性改善力が行われるものであ
る。
Although titanium silicide is used for the source and drain parts, and titanium nitride is used as the barrier metal, other silicides can be used for the gate (for example, molybdenum polycide or usually only polysilicon), the source, and the drain. For example, zirconium silicide) is of course possible, and titanium tungsten is also effective as the barrier metal. The point is that the layered structure of the barrier metal and tungsten CVD provides the basic ability to improve characteristics.

以上述べてきたように、本発明は超高速、高集積、高信
頼性デバイスを実現する為に不可決な配線手段を提供す
るものである。
As described above, the present invention provides an essential wiring means for realizing ultra-high speed, highly integrated, and highly reliable devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(α)〜<c>は、本発明デバイスの製造方法を
示した工程断面図。 第2図は、従来方法を示した断面図。 1・・・・・・・・−3i基板 2 ・・・・・・・・・ LOOO8 5・・・・・・・・・ゲート膜 4・・・・・・・・・リンドープポリシリコン5・・・
・・・・・・チタンシリサイド6・・・・・・・・・ラ
イトドーフ層 7・・・・・・・・・サイドウオール 8・・・・・・・・・チタンシリサイド9・・・・・・
・・・高濃度ジャンクシ、ン10・・・・・・層間絶縁
膜 11・・・・・・チタンナイトライド 12・・・・・・タングステンCVD膜13・・・・・
・AL膜 以上
FIGS. 1(α) to <c> are process cross-sectional views showing the method for manufacturing the device of the present invention. FIG. 2 is a sectional view showing a conventional method. 1......-3i substrate 2......LOOO8 5......gate film 4...phosphorus-doped polysilicon 5 ...
......Titanium silicide 6...Lightdorf layer 7...Side wall 8...Titanium silicide 9...・・・
... High concentration junk film 10 ... Interlayer insulating film 11 ... Titanium nitride 12 ... Tungsten CVD film 13 ...
・More than AL film

Claims (4)

【特許請求の範囲】[Claims] (1)半導体集積回路の製造において、ゲート電極を形
成する工程と、層間絶縁膜を形成する工程と、該層間絶
縁膜を、コンタクトフォトエッチングする工程を経た後
、バリアメタルとタングステンCVD膜を積層でデポジ
ションする工程と、該積層膜を、同時にフォトエッチン
グして配線層を形成することを特徴とした半導体装置の
製造方法
(1) In the manufacture of semiconductor integrated circuits, after passing through the steps of forming a gate electrode, forming an interlayer insulating film, and contact photo-etching the interlayer insulating film, a barrier metal and a tungsten CVD film are laminated. A method for manufacturing a semiconductor device, comprising: a step of depositing the layered film; and simultaneously photo-etching the laminated film to form a wiring layer.
(2)該バリアメタルと、タングステンCVD膜上にA
L系膜を形成し3層膜とすることを特徴とする特許請求
の範囲第1項記載の半導体装置の製造方法。
(2) A on the barrier metal and the tungsten CVD film.
A method for manufacturing a semiconductor device according to claim 1, characterized in that an L-based film is formed to form a three-layer film.
(3)該ゲート電極をSalicide(Self−a
lignedsllicide)電極とすることを特徴
とする特許請求の範囲第1項記載の半導体装置の製造方
法。
(3) The gate electrode is coated with Salicide (Self-a
2. The method of manufacturing a semiconductor device according to claim 1, wherein the electrode is a ligated sllicide electrode.
(4)該ゲート電極をSalicide電極とし、該バ
リアメタルとタングステンCVD膜上にAL系膜を形成
し3層膜とすることを特徴とする特許請求の範囲第1項
記載の半導体装置の製造方法。
(4) The method for manufacturing a semiconductor device according to claim 1, characterized in that the gate electrode is a salicide electrode, and an AL-based film is formed on the barrier metal and the tungsten CVD film to form a three-layer film. .
JP18250885A 1985-08-20 1985-08-20 Manufacture of semiconductor device Pending JPS6243175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18250885A JPS6243175A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18250885A JPS6243175A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6243175A true JPS6243175A (en) 1987-02-25

Family

ID=16119523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18250885A Pending JPS6243175A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6243175A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6427243A (en) * 1987-03-30 1989-01-30 Ibm Conductive structure for semiconductor device
JPH021925A (en) * 1987-12-02 1990-01-08 Philips Gloeilampenfab:Nv Manufacture of electric connector
US5753534A (en) * 1992-11-06 1998-05-19 Hyundai Electronics Industries, Co., Ltd. Semiconductor connecting device and method for making the same
JP2002158354A (en) * 2000-11-17 2002-05-31 Sanyo Electric Co Ltd Insulated gate semiconductor device and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6427243A (en) * 1987-03-30 1989-01-30 Ibm Conductive structure for semiconductor device
JPH021925A (en) * 1987-12-02 1990-01-08 Philips Gloeilampenfab:Nv Manufacture of electric connector
US5753534A (en) * 1992-11-06 1998-05-19 Hyundai Electronics Industries, Co., Ltd. Semiconductor connecting device and method for making the same
JP2002158354A (en) * 2000-11-17 2002-05-31 Sanyo Electric Co Ltd Insulated gate semiconductor device and method of manufacturing the same

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