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JPS6234716B2 - - Google Patents

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Publication number
JPS6234716B2
JPS6234716B2 JP56116008A JP11600881A JPS6234716B2 JP S6234716 B2 JPS6234716 B2 JP S6234716B2 JP 56116008 A JP56116008 A JP 56116008A JP 11600881 A JP11600881 A JP 11600881A JP S6234716 B2 JPS6234716 B2 JP S6234716B2
Authority
JP
Japan
Prior art keywords
film
crystal
substrate
polycrystalline
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56116008A
Other languages
Japanese (ja)
Other versions
JPS5820794A (en
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP56116008A priority Critical patent/JPS5820794A/en
Priority to NLAANVRAGE8202526,A priority patent/NL188550C/en
Priority to GB08218306A priority patent/GB2104723B/en
Priority to DE19823224604 priority patent/DE3224604A1/en
Publication of JPS5820794A publication Critical patent/JPS5820794A/en
Priority to US06/723,708 priority patent/US4576851A/en
Publication of JPS6234716B2 publication Critical patent/JPS6234716B2/ja
Priority to HK890/87A priority patent/HK89087A/en
Priority to US07/171,370 priority patent/USRE33096E/en
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Description

【発明の詳細な説明】 本発明は、半導体基板の製造方法に関し、とり
わけ絶縁体上の単結晶Si膜の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a single crystal Si film on an insulator.

従来から絶縁体上の単結晶半導体膜の製造方法
としては通常SOS（Silicon On Sapphire）に代
表される。単結晶サフアイヤ基板上にSi半導体膜
を席ピタキシヤル法で形成する方法がある。 SOS (Silicon On Sapphire) is the conventional method for manufacturing single crystal semiconductor films on insulators. There is a method of forming a Si semiconductor film on a single-crystal sapphire substrate by a Si-pitaxial method.

しかし、前記従来技術では、育成された単結晶
Si膜の格子間定数と基板サフアイヤ単結晶の格子
間定数と完全に一致する結晶面がなく、せいぜい
数％の格子定数差におさめるのが最良であるため
に、単結晶Si膜に結晶欠陥が多いと云う欠点があ
る。 However, in the conventional technology, the grown single crystal
Since there is no crystal plane that perfectly matches the interstitial constant of the Si film and the interstitial constant of the Saphire single crystal substrate, and it is best to keep the lattice constant difference to a few percent at most, crystal defects occur in the single crystal Si film. There are many drawbacks.

さらに、前記サフアイヤ基板が高価であり、こ
の様な絶縁体上の単結晶半導体膜を用いて高速の
半導体装置を製作する事への要望が大きいにも拘
らず、実用化が遅れている。 Furthermore, the sapphire substrate is expensive, and although there is a strong desire to manufacture high-speed semiconductor devices using such a single crystal semiconductor film on an insulator, its practical implementation has been delayed.

本発明はかかる欠点をなくし、低価格で結晶欠
陥の少ない絶縁体上に半導体単結晶膜を形成した
高速の半導体装置用の半導体基板の製造方法を提
供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and to provide a method for manufacturing a semiconductor substrate for a high-speed semiconductor device in which a semiconductor single crystal film is formed on an insulator with low cost and few crystal defects.

上記目的を達成するための本発明の基本的な構
成は、第１の固体表面の端部には第２の固体単結
晶からなる単結晶育成種が設けられ、該固体単結
晶育成種に少なくとも接して成り、且つ第１の固
体表面を被覆した多結晶またはアモルフアス状態
の第２と同一材料からなる膜または第３の固体材
料膜が形成されて成つた基板を形成し、該基板を
前記固体材料膜の融点よりわずかに低温に保ちな
がら少なくとも前記固体単結晶育成種と前記固体
材料膜とが接した部分から電子線あるいは光線等
のエネルギービームを照射して融解しながら移動
走査し、前記エネルギービームにより第１の固体
表面上の前記固体材料膜や実質的に連続して融解
と冷却過程による固体化による単結晶化を行な
い、前記固体材料膜を基板表面において単結晶化
することを特徴とする。 The basic configuration of the present invention for achieving the above object is that a single crystal growth seed consisting of a second solid single crystal is provided at the end of the first solid surface, and the solid single crystal growth seed is provided with at least one solid single crystal growth seed. forming a substrate on which a film made of the same material as the second solid material or a third solid material film in a polycrystalline or amorphous state is formed, which is in contact with the surface of the first solid material and coated on the surface of the first solid material; While keeping the temperature slightly lower than the melting point of the material film, an energy beam such as an electron beam or a light beam is irradiated from at least the portion where the solid single crystal growth seed and the solid material film are in contact with each other, and the energy beam is moved and scanned while melting. The method is characterized in that the solid material film on the first solid surface is solidified into a single crystal by a substantially continuous melting and cooling process by the beam, and the solid material film is single crystallized on the substrate surface. do.

以下、実施例を用いて本発明を詳細に述べる。 The present invention will be described in detail below using examples.

第１図は本発明の実施例を模式的に示したもの
で、１はカーボン・ヒーターであり、1200℃〜
1300℃に通電して保たれる。該カーボン・ヒータ
上には試料がのせられ、該試料は単結晶Si基板２
の大部分がSiO2膜、Si3N4膜あるいはSiO2とSi3N4
膜の２層構造膜等の絶縁膜３により被覆され、該
絶縁膜３の一部がエツチングにより窓開けされ、
下地単結晶Si基板２をその端部において露出さ
せ、該露出単結晶Si基板部を単結晶Si膜の育成種
部分４となし、それらの表面には多結晶Si膜５が
CVD法により形成され、該多結晶Si膜５と接触
している単結晶Si基板２と連続する単結晶育成種
４の部分に電子線あるいはレーザー光線等のエネ
ルギービーム６をＸ方向に実質的に線状に照射し
て、多結晶Si膜５を部分的に1400℃程度で融解し
ながら、Ｙ方向に移動せしめることにより、融解
した多結晶Siが冷却過程で単結晶化した部分７が
Ｙ方向に連続して成長し、多結晶Si膜５は全面単
結晶Si膜となる。 Fig. 1 schematically shows an embodiment of the present invention, in which 1 is a carbon heater, and the temperature is 1200℃~
Electrified and maintained at 1300℃. A sample is placed on the carbon heater, and the sample is placed on a single crystal Si substrate 2.
Most of the film is SiO 2 film, Si 3 N 4 film, or SiO 2 and Si 3 N 4
It is covered with an insulating film 3 such as a two-layer structure film, and a part of the insulating film 3 is etched to open a window.
The base single-crystal Si substrate 2 is exposed at its end, and the exposed single-crystal Si substrate portion is used as a growth seed portion 4 for a single-crystal Si film, and a polycrystalline Si film 5 is formed on the surface thereof.
An energy beam 6 such as an electron beam or a laser beam is applied to a portion of the single crystal growth seed 4 formed by the CVD method and continuous with the single crystal Si substrate 2 that is in contact with the polycrystalline Si film 5 in the X direction. By moving the polycrystalline Si film 5 in the Y direction while partially melting it at about 1400°C, the portion 7 where the melted polycrystalline Si has become a single crystal in the cooling process is irradiated in the Y direction. The polycrystalline Si film 5 grows continuously and becomes a single-crystalline Si film over the entire surface.

この様にして形成された絶縁体上の単結晶Si膜
は育成種の結晶性がそのまま保持された単結晶膜
となり、結晶欠陥が少なく、且つ基板がサフアイ
ヤの如く高価なものである必要はなく、低価格で
かつ高速半導体組子製作に適した基板が提供でき
るという効果がある。 The single-crystal Si film on the insulator formed in this way is a single-crystal film that maintains the crystallinity of the grown seed, has few crystal defects, and does not need to be an expensive substrate like saphire. This has the effect of providing a low-cost substrate suitable for high-speed semiconductor muntin manufacturing.

上述の如く本発明は、単結晶Si基板の端部にそ
の単結晶Si基板と連続する単結晶育成種を設け、
この単結晶育成種に少なくとも接してなり、単結
晶Si基板を被覆した多結晶またはアモルフアス状
態のSi膜を形成する。その後、少なくとも多結晶
またはアモルフアス状態のSi膜をその融点よりも
わずかに低く加熱し、電子線または光線等のエネ
ルギービームを、単結晶Si基板の端部にその単結
晶Si基板と連続するように形成された単結晶育成
種の上のSi膜から照射を開始し、Si膜全体にわた
つて移動走査されるので、Si膜自体が高温に維持
されつつ、エネルギービーム照射で単結晶化がは
かられ、低消費電力のエネルギービームを用いて
均質な単結晶Si膜の育成が可能となる。また、単
結晶育成種を単結晶Si基板と連続するように単結
晶Si基板の端部に設けたので、その単結晶育成種
上に形成された多結晶またはアモルフアス状態の
Si膜からエネルギービームの照射を開始し、Si膜
全体にわたつて移動走査するので、簡単に広い面
積を有する単結晶Si膜が確実に得られるのであ
る。 As described above, the present invention provides a single-crystal growth seed continuous with the single-crystal Si substrate at the edge of the single-crystal Si substrate,
A polycrystalline or amorphous Si film is formed in at least contact with this single crystal growth seed and covering the single crystal Si substrate. Thereafter, the Si film in at least a polycrystalline or amorphous state is heated to a temperature slightly lower than its melting point, and an energy beam such as an electron beam or a light beam is applied to the edge of the single crystal Si substrate so as to be continuous with the single crystal Si substrate. Irradiation starts from the Si film above the formed single crystal growth seed and is moved and scanned over the entire Si film, so the Si film itself is maintained at a high temperature and the energy beam irradiation prevents single crystallization. This makes it possible to grow homogeneous single-crystal Si films using energy beams with low power consumption. In addition, since the single-crystal growth seed was provided at the edge of the single-crystal Si substrate so as to be continuous with the single-crystal Si substrate, the polycrystalline or amorphous state formed on the single-crystal growth seed
Since the energy beam irradiation starts from the Si film and moves and scans over the entire Si film, a single crystal Si film with a wide area can be easily and reliably obtained.

さらに、単結晶育成種を単結晶Si基板の端部
に、その単結晶Si基板と連続するように設けたの
で、この単結晶育成種を用いて多結晶またはアモ
ルフアス状態のSi膜を単結晶Si膜とした時に、こ
の単結晶Si膜は、その成長の基となつた単結晶Si
基板と結晶面がそろうから、それぞれ、単結晶Si
基板と単結晶Si膜に半導体装置つまり素子等を形
成しても、非常に素子特性の等しい素子が形成で
きるものである。よつて半導体装置全体の信頼性
が非常に高いものとなる。 Furthermore, since a single crystal growth seed was provided at the edge of the single crystal Si substrate so as to be continuous with the single crystal Si substrate, this single crystal growth seed was used to grow a polycrystalline or amorphous Si film onto the single crystal Si substrate. When formed into a film, this single-crystal Si film grows from the single-crystal Si that was the basis of its growth.
Since the crystal planes are aligned with the substrate, each single-crystal Si
Even if a semiconductor device, ie, an element, etc. is formed on a substrate and a single-crystal Si film, it is possible to form an element with very similar device characteristics. Therefore, the reliability of the entire semiconductor device becomes extremely high.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例による半導体基板を模
式的に示した斜視図である。 １……カーボン・ヒーター、２……単結晶Si基
板、３……絶縁膜、４……単結晶育成種部分、５
……多結晶Si膜、６……エネルギービーム、７…
…単結晶Si膜。 FIG. 1 is a perspective view schematically showing a semiconductor substrate according to an embodiment of the present invention. 1...Carbon heater, 2...Single crystal Si substrate, 3...Insulating film, 4...Single crystal growth seed part, 5
...Polycrystalline Si film, 6...Energy beam, 7...
...Single crystal Si film.

Claims (1)

【特許請求の範囲】[Claims] １ 単結晶Si基板の端部に前記単結晶Si基板と連
続する単結晶育生種となる領域を形成する工程、
前記単結晶育成種の領域以外の前記単結晶Si基板
の上に絶縁膜を形成する工程、前記単結晶育成種
上及び前記絶縁膜上に、少なくとも前記単結晶育
成種に接するように多結晶またはアモルフアス状
態のSi膜を形成する工程、前記多結晶またはアモ
ルフアス状態のSi膜をその融点よりもわずかに低
く保持するべく加熱する工程、前記単結晶育成種
上の加熱された前記多結晶またはアモルフアス状
態のSi膜に電子線または光線等のエネルギービー
ムを照射する工程、前記単結晶育成種上に形成さ
れた前記多結晶またはアモルフアス状態のSi膜か
ら前記絶縁膜上に形成された前記多結晶またはア
モルフアス状態のSi膜全体に前記エネルギービー
ムを移動走査して、前記多結晶またはアモルフア
ス状態のSi膜を単結晶Si膜とする工程を有するこ
とを特徴とする半導体基板の製造方法。1. Forming a region continuous with the single-crystal Si substrate and serving as a single-crystal growth seed at the end of the single-crystal Si substrate;
forming an insulating film on the single-crystal Si substrate other than the area of the single-crystal growth seed; forming a polycrystalline or forming an amorphous Si film; heating the polycrystalline or amorphous Si film to maintain it slightly below its melting point; heating the polycrystalline or amorphous Si film on the single crystal growth seed; A step of irradiating the Si film with an energy beam such as an electron beam or a light beam, and converting the polycrystalline or amorphous Si film formed on the single crystal growth seed to the polycrystalline or amorphous Si film formed on the insulating film. 1. A method for manufacturing a semiconductor substrate, comprising a step of moving and scanning the energy beam over the entire Si film in a state to convert the Si film in a polycrystalline or amorphous state into a single crystal Si film.
JP56116008A 1981-07-02 1981-07-24 Manufacturing method of semiconductor substrate Granted JPS5820794A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP56116008A JPS5820794A (en) 1981-07-24 1981-07-24 Manufacturing method of semiconductor substrate
NLAANVRAGE8202526,A NL188550C (en) 1981-07-02 1982-06-22 METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE
GB08218306A GB2104723B (en) 1981-07-02 1982-06-24 Semiconductor substrate and method of manufacturing the same
DE19823224604 DE3224604A1 (en) 1981-07-02 1982-07-01 SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING A MONOCRISTALLINE LAYER
US06/723,708 US4576851A (en) 1981-07-02 1985-04-16 Semiconductor substrate
HK890/87A HK89087A (en) 1981-07-24 1987-11-26 Method of manufacturing semiconductor substrate and substrate so manufactured
US07/171,370 USRE33096E (en) 1981-07-02 1988-03-17 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56116008A JPS5820794A (en) 1981-07-24 1981-07-24 Manufacturing method of semiconductor substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP9943888A Division JPS63285184A (en) 1988-04-22 1988-04-22 Method for manufacturing single crystal film

Publications (2)

Publication Number Publication Date
JPS5820794A JPS5820794A (en) 1983-02-07
JPS6234716B2 true JPS6234716B2 (en) 1987-07-28

Family

ID=14676540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56116008A Granted JPS5820794A (en) 1981-07-02 1981-07-24 Manufacturing method of semiconductor substrate

Country Status (2)

Country Link
JP (1) JPS5820794A (en)
HK (1) HK89087A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051688A (en) * 1983-08-29 1985-03-23 Nippon Hoso Kyokai <Nhk> Impurity segregation method
JPS60159631U (en) * 1984-04-03 1985-10-23 株式会社　オリエント総業 Marking device for strips

Also Published As

Publication number Publication date
JPS5820794A (en) 1983-02-07
HK89087A (en) 1987-12-04

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