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JPS6233778B2 - - Google Patents

Info

Publication number
JPS6233778B2
JPS6233778B2 JP56154604A JP15460481A JPS6233778B2 JP S6233778 B2 JPS6233778 B2 JP S6233778B2 JP 56154604 A JP56154604 A JP 56154604A JP 15460481 A JP15460481 A JP 15460481A JP S6233778 B2 JPS6233778 B2 JP S6233778B2
Authority
JP
Japan
Prior art keywords
circuit
signal
amplifier
incoming signal
detection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56154604A
Other languages
Japanese (ja)
Other versions
JPS5856540A (en
Inventor
Isao Nakazawa
Masaharu Akutsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56154604A priority Critical patent/JPS5856540A/en
Publication of JPS5856540A publication Critical patent/JPS5856540A/en
Publication of JPS6233778B2 publication Critical patent/JPS6233778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3005Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Measurement Of Current Or Voltage (AREA)

Description

【発明の詳細な説明】 本発明は着信信号レベル対検出出力レベルの直
線性を良くした着信信号レベル検出回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an incoming signal level detection circuit that improves the linearity of incoming signal level versus detected output level.

マイクロ波、ミリ波等による無線通信において
その通信状態のモニターのため、受信側で着信信
号レベルを検出する必要性があるが、その方法と
しては次のようなものがある。
In wireless communication using microwaves, millimeter waves, etc., in order to monitor the communication status, it is necessary to detect the level of an incoming signal on the receiving side, and the following methods are available for this purpose.

その1つは受信機内の複数の可変利得増幅器の
うちの適切な可変利得増幅器の出力信号を検波し
てこれを着信信号レベルの検出出力信号とする方
法である。この方法によると、着信信号レベル対
検出出力信号の直線性が悪くてそのモニターに不
都合を来たすという欠点を有する。
One method is to detect the output signal of a suitable variable gain amplifier among a plurality of variable gain amplifiers in the receiver and use this as a detection output signal of the incoming signal level. This method has the disadvantage that the linearity of the incoming signal level versus the detected output signal is poor, causing inconvenience to the monitor.

また、レベル検波回路の出力に対数増幅器を接
続して直線性を改善するという方法もあるが、こ
の方法によると、その回路構成が複雑となりコス
ト高になつてしまう。
There is also a method of connecting a logarithmic amplifier to the output of the level detection circuit to improve linearity, but this method results in a complicated circuit configuration and high cost.

本発明は上述の如き従来回路の有する欠点に鑑
みて創案されたもので、その目的は着信信号レベ
ル対検出出力信号特性と着信信号レベル対自動利
得制御信号特性との相反性を利用して到来した着
信信号レベル対検出出力信号特性の直線性を良く
し、モニター機能の向上に資する着信信号レベル
検出回路を提供することにある。
The present invention was devised in view of the drawbacks of the conventional circuits as described above, and its purpose is to utilize the reciprocity between the incoming signal level versus detection output signal characteristic and the incoming signal level versus automatic gain control signal characteristic. It is an object of the present invention to provide an incoming signal level detection circuit that improves the linearity of the incoming signal level versus detected output signal characteristic and contributes to improving the monitoring function.

以下、添付図面を参照しながら本発明の一実施
例を説明する。
Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

第1図は本発明を実施した着信信号レベル検出
回路を示す。この回路1において、2,3,4,
5は増幅器、6,7,8は可変減衰器である。第
1段増幅器2の入力は入力端子9に接続されてい
る。最終段即ち第4段の増幅器5の出力と各可変
減衰器6,7,8の利得制御入力との間に検波器
10と自動利得制御回路11とがこの順で接続さ
れている。また、自動利得制御回路11の出力は
合成回路12の一方の入力へ接続されている。合
成回路12の他方の入力は第3段目の増幅器4の
出力に接続されたレベル検出回路例えば検波回路
13の出力に接続されている。合成回路12は例
えば、差動増幅回路であり、一方の入力信号と他
方の入力信号の反転信号とを合成して出力する回
路である。
FIG. 1 shows an incoming signal level detection circuit embodying the invention. In this circuit 1, 2, 3, 4,
5 is an amplifier, and 6, 7, and 8 are variable attenuators. The input of the first stage amplifier 2 is connected to an input terminal 9. A detector 10 and an automatic gain control circuit 11 are connected in this order between the output of the final or fourth stage amplifier 5 and the gain control input of each variable attenuator 6, 7, 8. Further, the output of the automatic gain control circuit 11 is connected to one input of the combining circuit 12. The other input of the synthesis circuit 12 is connected to the output of a level detection circuit, such as a detection circuit 13, which is connected to the output of the third stage amplifier 4. The synthesizing circuit 12 is, for example, a differential amplifier circuit, and is a circuit that synthesizes one input signal and an inverted signal of the other input signal and outputs the synthesized signal.

次に、上記構成の本発明回路の動作を説明す
る。
Next, the operation of the circuit of the present invention having the above configuration will be explained.

入力端子9へ到来した着信信号が増幅器2、可
変減衰器6、増幅器3、そして可変減衰器7を経
て増幅器4で増幅される。その出力信号はレベル
検出回路13へ供給されると共に可変減衰器8へ
供給される。
An incoming signal arriving at the input terminal 9 is amplified by the amplifier 4 via the amplifier 2, the variable attenuator 6, the amplifier 3, and the variable attenuator 7. The output signal is supplied to the level detection circuit 13 and also to the variable attenuator 8.

レベル検出回路13へ供給された上記信号は回
路13で検出処理例えば検波されて上記着信信号
に対する検出出力レベル信号を発生する。この検
出出力レベル信号は着信信号レベルに対し、第2
図の曲線L1で表わされるような特性を持つてい
る。
The signal supplied to the level detection circuit 13 is subjected to detection processing, for example, detection, to generate a detection output level signal for the incoming signal. This detection output level signal has a second level relative to the incoming signal level.
It has characteristics as shown by curve L1 in the figure.

他方、可変減衰器8へ供給された出力信号は増
幅器5で更に増幅された後、検波器10へ供給さ
れる。その検波出力信号は自動利得制御回路11
へ供給され、該回路から自動利得制御信号が発生
されて可変減衰器6,7,8の利得制御入力へ供
給されると共に合成回路12の一方の入力へ供給
される。この自動利得制御信号は着信信号レベル
に対し、第2図の曲線L2で示すような特性を持
つている。
On the other hand, the output signal supplied to the variable attenuator 8 is further amplified by the amplifier 5 and then supplied to the detector 10. The detection output signal is the automatic gain control circuit 11
from which an automatic gain control signal is generated and applied to the gain control inputs of the variable attenuators 6, 7, 8 and to one input of the combining circuit 12. This automatic gain control signal has characteristics as shown by curve L2 in FIG. 2 with respect to the incoming signal level.

上述の両信号は合成回路12において合成され
る。これを具体的に説明すると、差動増幅回路1
2の反転入力へ供給された検出出力信号は実効的
に反転されて回路12の非反転入力へ供給された
自動利得制御信号に加算される。この動作を第2
図を用いて説明すると、その動作は曲線L1で表
わされる検出出力信号の極性を反転した信号を表
わす曲線L3と曲線L2とを合成して曲線L4に
することに相当する。これより、明らかな如く、
着信信号レベルに対する合成回路12の出力信
号、即ち本発明回路の検出出力信号の直線性が大
幅に改善される。また、合成回路として差動増幅
器を用いると、上述の如くそれ自身で極性反転が
出来る外、負荷条件(例えば、インピーダンス、
レベル)を任意に選べる。
Both signals mentioned above are combined in the combining circuit 12. To explain this specifically, differential amplifier circuit 1
The detection output signal applied to the inverting input of circuit 12 is effectively inverted and added to the automatic gain control signal applied to the non-inverting input of circuit 12. Repeat this operation as a second
To explain using a diagram, the operation corresponds to combining a curve L3 and a curve L2, which represent a signal with the polarity of the detection output signal represented by the curve L1 inverted, to form a curve L4. From this, it is clear that
The linearity of the output signal of the combining circuit 12, ie the detection output signal of the circuit of the invention, with respect to the incoming signal level is significantly improved. In addition, when a differential amplifier is used as a synthesis circuit, it can perform polarity reversal by itself as described above, and it also allows for load conditions (for example, impedance,
level) can be selected arbitrarily.

上記実施例においては合成回路として差動増幅
回路を用いる例について説明したが、他方の入力
へ供給される信号を反転回路へ供給し、その出力
信号と一方の入力へ供給される信号とを抵抗和回
路へ供給するように構成してもよい。
In the above embodiment, an example was explained in which a differential amplifier circuit is used as a combining circuit, but the signal supplied to the other input is supplied to an inverting circuit, and the output signal and the signal supplied to one input are connected to each other by a resistor. It may also be configured to be supplied to a sum circuit.

また検波回路として、ピーク検波回路、平均値
検波回路、包絡線検波回路の構成のいずれであつ
てもよい。
Further, the detection circuit may have a configuration of a peak detection circuit, an average value detection circuit, or an envelope detection circuit.

以上の説明から明らかなように、本発明によれ
ば、次のような効果が得られる。
As is clear from the above description, according to the present invention, the following effects can be obtained.

着信レベル検出特性の直線性が改善される。 The linearity of the incoming level detection characteristic is improved.

従つて、着信レベルモニター回路のスレツシ
ヨールド値を正確に設定出来るし、感度の一定
性が得られることから広範囲な着信信号レベル
に対し高精度のモニターリングが行える。又、
着信レベルに応じて決まる送信自動利得制御を
かける通信方式においては、誤差の少ない送信
制御が行える。
Therefore, the threshold value of the incoming signal level monitor circuit can be set accurately, and sensitivity can be kept constant, so that highly accurate monitoring can be performed over a wide range of incoming signal levels. or,
In a communication system that applies automatic transmission gain control determined according to the incoming signal level, transmission control can be performed with few errors.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の着信信号レベル検出回路図、
第2図は着信信号レベル対各種出力レベルの特性
曲線図である。 図中、4,5は増幅器、11は自動利得制御回
路、13はレベル検出回路、12は合成回路であ
る。
FIG. 1 is an incoming signal level detection circuit diagram of the present invention;
FIG. 2 is a characteristic curve diagram of incoming signal level versus various output levels. In the figure, 4 and 5 are amplifiers, 11 is an automatic gain control circuit, 13 is a level detection circuit, and 12 is a synthesis circuit.

Claims (1)

【特許請求の範囲】 1 増幅器を有する着信信号レベル検出回路にお
いて上記増幅器の出力に接続されたレベル検出回
路と、上記増幅器の出力へ接続された自動利得制
御回路と、上記レベル検出回路及び自動利得制御
回路の出力信号のうちの一方の信号を反転し、そ
の反転信号を他方の信号と合成する合成回路とよ
り成る着信信号レベル検出回路。 2 上記合成回路を差動増幅回路で構成したこと
を特徴とする特許請求の範囲第1項記載の着信信
号レベル検出回路。
[Claims] 1. In an incoming signal level detection circuit having an amplifier, a level detection circuit connected to the output of the amplifier, an automatic gain control circuit connected to the output of the amplifier, the level detection circuit and the automatic gain An incoming signal level detection circuit comprising a combining circuit that inverts one of the output signals of the control circuit and combines the inverted signal with the other signal. 2. The incoming signal level detection circuit according to claim 1, wherein the combining circuit is constructed of a differential amplifier circuit.
JP56154604A 1981-09-29 1981-09-29 Detecting circuit for incoming signal level Granted JPS5856540A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56154604A JPS5856540A (en) 1981-09-29 1981-09-29 Detecting circuit for incoming signal level

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56154604A JPS5856540A (en) 1981-09-29 1981-09-29 Detecting circuit for incoming signal level

Publications (2)

Publication Number Publication Date
JPS5856540A JPS5856540A (en) 1983-04-04
JPS6233778B2 true JPS6233778B2 (en) 1987-07-22

Family

ID=15587807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56154604A Granted JPS5856540A (en) 1981-09-29 1981-09-29 Detecting circuit for incoming signal level

Country Status (1)

Country Link
JP (1) JPS5856540A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258738A (en) * 2007-04-02 2008-10-23 Mitsubishi Electric Corp Detection logarithmic amplifier
CN105182062A (en) * 2015-10-22 2015-12-23 江苏绿扬电子仪器集团有限公司 High-precision wideband and wide-alternating-current millivoltmeter

Also Published As

Publication number Publication date
JPS5856540A (en) 1983-04-04

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