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JPS6230418A - Analog multiplexer - Google Patents

Analog multiplexer

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Publication number
JPS6230418A
JPS6230418A JP17017585A JP17017585A JPS6230418A JP S6230418 A JPS6230418 A JP S6230418A JP 17017585 A JP17017585 A JP 17017585A JP 17017585 A JP17017585 A JP 17017585A JP S6230418 A JPS6230418 A JP S6230418A
Authority
JP
Japan
Prior art keywords
input
analog
circuit
output
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17017585A
Other languages
Japanese (ja)
Inventor
Yoshiaki Fujii
藤井 義昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP17017585A priority Critical patent/JPS6230418A/en
Publication of JPS6230418A publication Critical patent/JPS6230418A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the electric insulating efficiency of an I/O stage and to attain high speed operation by forming an I/O separating circuit having plural contact relays, a high speed switching circuit having plural semiconductor analog switches and a control circuit. CONSTITUTION:The I/O separating circuit 10 is constituted of plural input terminals A1-An to which analog voltages are impressed from the external, plural contact relays D1-Dn, and so on. The high speed switching circuit 12 is constituted of plural input terminals E1-En connected to respective output terminals of the circuit 10 and plural semiconductor analog switches G1-Gn. In the switching operation of analog input voltages Vi (i=1-n) in the n system, all capacitors Ci connected to all input terminals Ai are simultaneously switched by all relays Di, then all input voltages Vi are applied to all output terminals Bi. Then, the analog switches Gi are successively turned on one by one and the voltages Vi are successively inputted to a gain amplifier 16. Consequently, the electric insulating efficiency of the I/O stage can be improved and high speed operation can be attained.

Description

【発明の詳細な説明】 A、産業上の利用分野 この発明は、例えば複数のアナログ入力を時分割で1つ
のA/D変換器に供給する場合などに利用されるアナロ
グマルチプレクサに関する。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to an analog multiplexer used, for example, when supplying a plurality of analog inputs to one A/D converter in a time-sharing manner.

B6発明の概要 この発明は、複数のアナログ入力電圧を電圧記憶用コン
デンサと有接点リレーを用いた人出力分順回路を介して
後段に一斉に伝え、それを半導体アナログスイッチを用
いた高速切換回路によって択一的に共通出力端に導出す
る構成とし、外部回路と入力段との電気的絶縁性と高速
動作の両方を実現した。
B6 Summary of the Invention This invention transmits multiple analog input voltages all at once to a subsequent stage via a human output dividing circuit using a voltage storage capacitor and a contact relay, and transfers the voltage to a high-speed switching circuit using a semiconductor analog switch. The configuration is such that it is selectively led out to a common output terminal, achieving both electrical isolation between the external circuit and the input stage and high-speed operation.

C1従来の技術 アナログマルチプレクサは、FET(電界効果トランジ
ス)などによる半導体アナログスイッチで複数の入力を
切換える無接点方式のものと、有接点リレーによって複
数の入力を切換える有接点方式のものとに大別される。
C1 Conventional technology Analog multiplexers are broadly divided into non-contact type types that switch multiple inputs using semiconductor analog switches such as FETs (field effect transistors), and contact type types that use contact relays to switch multiple inputs. be done.

D0発明が解決しようとする問題点 無接点方式のアナログマルチプレクサは、アナログスイ
ッチのスイッチング速度が極めて速いので、切換動作を
容易に高速化できる。しかし、入出力段がアナログスイ
ッチを介して常時接続されているため、電気的絶縁性を
高くできず、外部回路の異常高電圧が内部回路や後段回
路(A / D変換器など)に直接的に影響し、外的要
因になる障害が発生しやすい。
D0 Problems to be Solved by the Invention In the non-contact type analog multiplexer, the switching speed of the analog switch is extremely fast, so the switching operation can be easily increased in speed. However, because the input and output stages are always connected via analog switches, it is not possible to provide high electrical insulation, and abnormally high voltages from external circuits can directly reach internal circuits and subsequent circuits (A/D converters, etc.). It is easy for failures caused by external factors to occur.

有接点方式のアナログマルチプレクサは、入力段と出力
段とがリレー接点で完全に分離する構成になるので、電
気的な絶縁性は高く、外的要因による内部回路の障害は
発生しにくい。しかし有接点のスイッチング速度は半導
体スイッチに比べて非常に遅いので、高速な多入力切換
えは行なえない。
A contact type analog multiplexer has a configuration in which the input stage and output stage are completely separated by relay contacts, so electrical insulation is high and internal circuit failures due to external factors are less likely to occur. However, since the switching speed of contacts is much slower than that of semiconductor switches, high-speed multi-input switching cannot be performed.

ところでプロセスコントローラ等においては、様々な対
象機器から採取した多数のアナログ信号をディジタル信
号がするのに、多数のA/D変換器を使用するのではな
くて、多数のアナログ信号をアナログマルチプレクサで
順番に切換えて1つのA/D変換器に入力し、時分割で
A/D変換を行なう構成が一般的である。
By the way, in process controllers, etc., many analog signals collected from various target devices are converted into digital signals, but instead of using many A/D converters, many analog signals are converted into digital signals using an analog multiplexer. A common configuration is to switch the signal to one A/D converter and perform A/D conversion in a time-division manner.

上記のような用途では、アナログマルチプレクサには高
速動作が強く要求されるとともに、様々な外部回路に対
する電気的絶縁性も重要になる。
In the above-mentioned applications, analog multiplexers are strongly required to operate at high speed, and electrical isolation from various external circuits is also important.

従来のいずれのアナログスイッチもこれらの要求を充分
に満たすことができない。
None of the conventional analog switches can satisfactorily meet these demands.

この発明は上述した従来の問題点に鑑みなされたもので
、その目的は、入出力段の電気的絶縁性が高く、かつ高
速動作が可能なアナログマルチプレクサを提供すること
にある。
The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide an analog multiplexer that has high electrical insulation between input and output stages and is capable of high-speed operation.

E0問題点を解決するための手段 この発明に係るアナログマルチプレクサは、入出力分離
回路と高速切換回路と制御回路とからなる。入出力分離
回路は、外部からアナログ電圧が印加される複数の入力
端と、これら入力端のそれぞれに対応した複数の電圧記
憶用コンデンサおよび複数の出力端と、上記各コンデン
サを上記入力端と上記出力端とに切換接続する複数の有
接点リレーとからなる。上記高速切換回路は、上記入出
力回路の各出力端にそれぞれ接続された複数の入力端と
、1つの共通出力端と、これら各入力端と共通出力端と
の間にそれぞれ接続された複数の半導体アナログスイッ
チとからなる。上記制御回路は、上記入出力分離回路に
おける上記各有接点リレーを同時に駆動して上記各コン
デンサを上記入力端から上記出力端に一斉に切換接続し
、その後上記高速切換回路における上記各アナログスイ
ツチを順番に1つずつオンさせる。
Means for Solving the E0 Problem The analog multiplexer according to the present invention includes an input/output separation circuit, a high-speed switching circuit, and a control circuit. The input/output separation circuit includes a plurality of input terminals to which analog voltages are applied from the outside, a plurality of voltage storage capacitors corresponding to each of these input terminals, a plurality of output terminals, and a plurality of capacitors connected to the input terminal and the output terminal. It consists of a plurality of contact relays that are switched and connected to the output terminal. The high-speed switching circuit has a plurality of input terminals respectively connected to each output terminal of the input/output circuit, one common output terminal, and a plurality of input terminals respectively connected between each of these input terminals and the common output terminal. Consists of a semiconductor analog switch. The control circuit simultaneously drives each of the contact relays in the input/output separation circuit to switch and connect each of the capacitors from the input terminal to the output terminal at the same time, and then drives each of the analog switches in the high-speed switching circuit. Turn them on one by one in order.

F1作用 上記入出力分離回路の有接点リレーによって外部回路と
内部回路とが良好に分離され、高い絶縁性が得られる。
Due to the F1 function, the external circuit and the internal circuit are well separated by the contact relay of the input/output separation circuit, and high insulation is obtained.

この有接点リレーのスイッチング速度は遅いが、切換動
作の1周期に1回しか切換わらないので、全体の動作時
間に与える影響は小さい。複数の入力を順次切換えるの
は上記アナログスイッチで高速に行なわれる。
Although the switching speed of this contact relay is slow, since it switches only once per cycle of switching operation, the effect on the overall operating time is small. Sequential switching of a plurality of inputs is performed at high speed using the analog switch.

G、実施例 第1図はこの発明に係るアナログマルチプレクサを応用
したデータ処理装置を示している。図において、入出力
分離回路10と高速切換回路12と制御回路14とでこ
の発明のアナログマルチプレクサが構成されており、こ
れで切換選択されアナログ信号がゲインアンプ16を経
てA/D変換器18に入力され、ディジタル化された信
号がデータ処理用のマイクロプロセッサ20に取り込ま
れる。制御回路14はプロセッサ20の指令を受けて動
作し、マルチプレクサの切換動作とA/D変換器18の
変換動作とを同期させる。
G. Embodiment FIG. 1 shows a data processing device to which an analog multiplexer according to the present invention is applied. In the figure, an analog multiplexer of the present invention is configured by an input/output separation circuit 10, a high-speed switching circuit 12, and a control circuit 14. The analog multiplexer of the present invention is switched and selected by the input/output separation circuit 10, and the analog signal is sent to the A/D converter 18 via the gain amplifier 16. The input and digitized signals are taken into a microprocessor 20 for data processing. The control circuit 14 operates in response to instructions from the processor 20 and synchronizes the switching operation of the multiplexer and the conversion operation of the A/D converter 18.

入出力分離回路10において、Ai(i= 1 、2 
、・・・。
In the input/output separation circuit 10, Ai (i=1, 2
,...

n)はn個の入力端、Bilよ入力端Aiに対応した出
力端、Ciは入出力端^i、 Biに対応した電圧記憶
用コンデンサ、DiはコンデンサCiを入力端Atと出
力端旧とに切換接続する有接点リレーである。
n) is the n input terminal, Bil is the output terminal corresponding to the input terminal Ai, Ci is the input/output terminal ^i, the voltage storage capacitor corresponding to Bi, and Di is the capacitor Ci between the input terminal At and the output terminal old. This is a contact relay that switches and connects to the

外部からのn系統のアナログ入力電圧Viがそれぞれ入
力端Aiに印加される。リレーDiでコンデンサCiが
入力端^iに接続されていると、コンデンサCiが充電
されてこれに入力端子viが記憶される。
N systems of analog input voltages Vi from the outside are respectively applied to the input terminals Ai. When the capacitor Ci is connected to the input terminal ^i by the relay Di, the capacitor Ci is charged and the input terminal vi is stored therein.

リレーDiが切換えられてコンデンサCiが出力端Bi
に接続されると、記憶された入力電圧Viが出力端Bi
に現われる。リレーDiの状態にかかわらず、入力端A
iと出力端Biとが完全に分離しているので、入出力間
の絶縁性は極めて高い。
Relay Di is switched and capacitor Ci is connected to output terminal Bi.
, the stored input voltage Vi is connected to the output terminal Bi
appears in Regardless of the state of relay Di, input terminal A
Since i and the output end Bi are completely separated, the insulation between input and output is extremely high.

高速切換回路12において、Eiはn個の入力端、Fは
1つの共通出力端、Giは各入力端Eiと共通出力端F
とをそれぞれ接続するFETアナログスイッチである。
In the high-speed switching circuit 12, Ei is n input terminals, F is one common output terminal, and Gi is each input terminal Ei and a common output terminal F.
This is an FET analog switch that connects the two.

なお、各入力端Eiの一方のラインは共通出力端Fの一
方のラインに共通に直結されている。
Note that one line of each input terminal Ei is directly connected to one line of the common output terminal F in common.

各入力端Eiは入出力分離回路10の各出力端Biと接
続され、共通出力端iは次段のゲインアンプ16の入力
端に接続されている。
Each input terminal Ei is connected to each output terminal Bi of the input/output separation circuit 10, and the common output terminal i is connected to the input terminal of a gain amplifier 16 at the next stage.

第2図のタイミングチャートに示すように、n系統のア
ナログ入力端子Viの切換動作の1周期は以下のとおり
である。
As shown in the timing chart of FIG. 2, one cycle of the switching operation of the n systems of analog input terminals Vi is as follows.

全コンデンサCiを全入力端Atに接続している状態か
ら全リレーDiを一斉に切換えて、全入力端子Viを全
出力端Biに導出する。一般的なリレーでは、この切換
えにはlOn+s程度の時間がかかる。
From a state in which all capacitors Ci are connected to all input terminals At, all relays Di are switched at once to lead out all input terminals Vi to all output terminals Bi. In a typical relay, this switching takes about 1On+s.

次に、アナログスイッチGiを順番に1つずつ、つまり
Gl、 G2.・・・、 Gnと1つずつオンにし、電
圧Vi、 V2.・・・、 Ynを順番にゲインアンプ
16に入力する。1つのアナログスイッチGiの動作時
間は100μs程度で、n個分ではnx tooμSで
ある。したがって1周期の切換動作時間はloa+s+
nX 100μsとなる。
Next, the analog switches Gi are turned on one by one, namely Gl, G2 . ..., Gn and turn on one by one, and the voltages Vi, V2 . ..., Yn are input to the gain amplifier 16 in order. The operating time for one analog switch Gi is about 100 μs, and for n analog switches Gi, it is nx too μS. Therefore, the switching operation time for one cycle is loa+s+
nX 100 μs.

なお、前述の有接点方式アナログマルチプレクサの場合
、nX 10m5もの時間がかかる。これに比べると本
発明のものははるかに高速である。
In addition, in the case of the above-mentioned contact type analog multiplexer, it takes as much time as nX 10m5. Compared to this, the method of the present invention is much faster.

H9発明の効果 以上詳細に説明したように、この発明に係るアナログマ
ルチプレクサは、従来の有接点方式のものと同じく入出
力間の高い絶縁性が得られ、外部・要因による内部回路
の障害は発生しにくい。また動作速度は、従来の有接点
方式のものよりはるかに速く、従来の無接点方式のもの
に近い。
H9 Effects of the Invention As explained in detail above, the analog multiplexer according to the present invention has the same high insulation between input and output as the conventional contact type, and there is no possibility of failure of the internal circuit due to external factors. It's hard to do. Moreover, the operating speed is much faster than that of conventional contact type and close to that of conventional non-contact type.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるアナログマルチプレ
クサを応用したデータ処理装置のブロック図、第2図は
同上マルチプレクサの動作を示すタイミングチャートで
ある。 10・・・入出力分離回路、At・・・入力端、旧・・
・出力端、Ci・・・コンデンサ、Di・・・有接点リ
レー、12・・・高速切換回路、Ei・・・入力端、F
・・・共通出力端、Gi・・・PETアナログスイッチ
、14・・・制御回路。
FIG. 1 is a block diagram of a data processing device using an analog multiplexer according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the same multiplexer. 10...Input/output separation circuit, At...input end, old...
・Output end, Ci...capacitor, Di...contact relay, 12...high speed switching circuit, Ei...input end, F
...Common output terminal, Gi...PET analog switch, 14...Control circuit.

Claims (1)

【特許請求の範囲】[Claims] (1)外部からアナログ電圧が印加される複数の入力端
と、これら各入力端のそれぞれに対応した複数の電圧記
憶用コンデンサおよび複数の出力端と、上記各コンデン
サを上記入力端と上記出力端とに切換接続する複数の有
接点リレーとからなる入出力分離回路と; 上記入出力分離回路の各出力端にそれぞれ接続された複
数の入力端と、1つの共通出力端と、これら各入力端と
共通出力端との間にそれぞれ接続された複数の半導体ア
ナログスイッチとからなる高速切換回路と; 上記入出力分離回路における上記各有接点リレーを同時
に駆動して上記各コンデンサを上記入力端から上記出力
端に一斉に切換接続し、その後上記高速切換回路におけ
る上記各アナログスイッチを順番に1つずつオンさせる
制御回路と; を備えたことを特徴とするアナログマルチプレクサ。
(1) A plurality of input terminals to which an analog voltage is applied from the outside, a plurality of voltage storage capacitors and a plurality of output terminals corresponding to each of these input terminals, and a plurality of capacitors connected to the input terminal and the output terminal. an input/output separation circuit consisting of a plurality of contact relays that are switched and connected to; a plurality of input terminals connected to each output terminal of the input/output separation circuit, one common output terminal, and each of these input terminals; a high-speed switching circuit consisting of a plurality of semiconductor analog switches respectively connected between the input terminal and the common output terminal; driving each of the contact relays in the input/output separation circuit simultaneously to switch each of the capacitors from the input terminal to the common output terminal; An analog multiplexer comprising: a control circuit that switches and connects the output terminals all at once, and then turns on each of the analog switches in the high-speed switching circuit one by one in sequence.
JP17017585A 1985-08-01 1985-08-01 Analog multiplexer Pending JPS6230418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17017585A JPS6230418A (en) 1985-08-01 1985-08-01 Analog multiplexer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17017585A JPS6230418A (en) 1985-08-01 1985-08-01 Analog multiplexer

Publications (1)

Publication Number Publication Date
JPS6230418A true JPS6230418A (en) 1987-02-09

Family

ID=15900082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17017585A Pending JPS6230418A (en) 1985-08-01 1985-08-01 Analog multiplexer

Country Status (1)

Country Link
JP (1) JPS6230418A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002139523A (en) * 2000-10-31 2002-05-17 Matsushita Electric Ind Co Ltd Stacked voltage measurement device
KR101067301B1 (en) 2008-04-25 2011-09-23 르네사스 일렉트로닉스 가부시키가이샤 Selective Signal Generation Method of Analog Multiplexer and Analog Multiplexer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4882759A (en) * 1972-02-05 1973-11-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4882759A (en) * 1972-02-05 1973-11-05

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002139523A (en) * 2000-10-31 2002-05-17 Matsushita Electric Ind Co Ltd Stacked voltage measurement device
KR101067301B1 (en) 2008-04-25 2011-09-23 르네사스 일렉트로닉스 가부시키가이샤 Selective Signal Generation Method of Analog Multiplexer and Analog Multiplexer

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