JPS6230337A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6230337A JPS6230337A JP16887685A JP16887685A JPS6230337A JP S6230337 A JPS6230337 A JP S6230337A JP 16887685 A JP16887685 A JP 16887685A JP 16887685 A JP16887685 A JP 16887685A JP S6230337 A JPS6230337 A JP S6230337A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- coated
- silicon dioxide
- cvd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000010408 film Substances 0.000 claims abstract description 28
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 8
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000013039 cover film Substances 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- 239000002904 solvent Substances 0.000 abstract description 2
- 230000001788 irregular Effects 0.000 abstract 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- -1 Phospho Chemical class 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- MDEGNXJQYYHASU-UHFFFAOYSA-N dioxosilane gold Chemical compound [Au].O=[Si]=O MDEGNXJQYYHASU-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路に関し、特に外部環境からの
素子の表面安定化（パッシベーション；ｐａｓｓｉｖａ
ｔｉｏｎ ）の為に設けられる。所謂表面保護膜（カバ
ー膜ともいう）Ｋ関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to surface stabilization (passivation) of elements from the external environment.
tion). This relates to a so-called surface protective film (also referred to as a cover film) K.
従来、この椙のカバー膜は、素子の最上層に形成される
、例えばｌ （アルミニウム）の配線パターン等の上か
ら、低温の常圧ＣＶＤ （ＣｈｅｍｉｃａｌＶａｐｏｒ
Ｄｅｐｏｓｉｔｉｏｎ ：化学的気相成長法）によっ
てＰＳＧ （Ｐｈｏｓｐｈｏ ５ｉｌｉｃａｔｅ Ｇｌ
ａｓｓ ）膜を被着したり、低温のプラズマＣＶＤ （
ＰｌａｓｍａＣＶＤ）によって窒化シリコン（ＳｉｘＮ
ｙ）膜′ｆｃ′ｆｉ着することによってなされて来ｆｃ
、、第２図にＰＳＧカバー膜の例を断面図で示す。基板
上の眉間絶縁膜の表面１の上のアルミ配線Ｇの上からＰ
ＳＧ７’を被着したものである。Conventionally, this cover film was formed using low-temperature atmospheric pressure CVD (Chemical Vapor
Deposition: PSG (Phospho 5ilicate Gl) by chemical vapor deposition method
ass) film or low-temperature plasma CVD (
Silicon nitride (SixN
y) made by attaching the membrane fc
,, FIG. 2 shows a cross-sectional view of an example of a PSG cover film. P from above the aluminum wiring G on the surface 1 of the glabella insulating film on the substrate
It is coated with SG7'.
これらのカバー膜は、素子の微細化に伴ってパターンの
密度が高くなる程表面の段差被覆性（ｓｔｅｐ ｃｏｖ
ｅｒａｇｅ ）が悪化し、段差部に膜厚の極端に薄い部
分が出来て機能低下したり、極端な場合にはそこが熱履
歴による応力集中或はその繰り返しによって割れ目とな
り用金成さなくなってしま１日する欠点がある。例えば
ＰＳＧ膜の場合。These cover films have improved surface step coverage as the pattern density increases with the miniaturization of devices.
(erage) deteriorates, and extremely thin parts are formed at the stepped parts, resulting in reduced functionality.In extreme cases, stress concentration due to thermal history or repetition of this process can lead to cracks, making it impossible for the film to be used. There are drawbacks to the day. For example, in the case of PSG film.
被覆性を向上するにはリン（ト）を全く添加しなければ
良いのだが、耐湿性が低下する為できない。In order to improve the coating properties, it would be better not to add phosphorus at all, but this is not possible because the moisture resistance would decrease.
本発明のカバー膜は、ＣＶＤにより被着されたリンを含
まない二酸化シリコン膜の第１層と、その上の凹凸部を
充填するシリカフィルムの第２層とを少くとも有してい
る。The cover film of the present invention has at least a first layer of phosphorus-free silicon dioxide film deposited by CVD and a second layer of silica film filling the irregularities thereon.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。樹脂或はセ
ラミック等による封止上する前の完成した素子の表面付
近を示す。Ａｆｉ配線２と、下層の導電層とを隔てる眉
間絶縁膜の表面１は、下地を反映して凹凸に描いである
。３は４００℃前後の常圧ＣＶＤにより被着された厚さ
３０００人の二酸化ケイ素の薄膜で％ ４は回転塗布さ
れｔ後、４００℃の熱処理によって溶剤を揮発させ、固
化させ之シリカフィルムで、二酸化ケイ素の薄膜３の凹
凸を埋めている。５はプラズマＣＶＤ により被着され
た厚さ５０００人の窒化ケイ素の薄膜であり、シリカフ
ィルム４によって全体の段差が軽減されているため、各
部の膜厚の均一性が良くなっている。FIG. 1 is a sectional view of an embodiment of the present invention. This figure shows the vicinity of the surface of a completed device before it is sealed with resin, ceramic, or the like. The surface 1 of the glabellar insulating film separating the Afi wiring 2 from the underlying conductive layer is uneven to reflect the underlying surface. 3 is a thin film of silicon dioxide with a thickness of 3,000% deposited by atmospheric pressure CVD at around 400°C; 4 is a silica film that is spin-coated and then heat treated at 400°C to volatilize the solvent and solidify; The unevenness of the silicon dioxide thin film 3 is filled in. 5 is a thin film of silicon nitride with a thickness of 5,000 wafers deposited by plasma CVD, and since the overall level difference is reduced by the silica film 4, the uniformity of the film thickness in each part is improved.
ここで、二酸化ケイ素の薄膜３は常圧ＣＶＤでなくとも
勿論よくて、減圧ＣＶＤ１用いることも可能であゆ、シ
リカフィルムにもリンを含有させずとも、又窒化ケイ素
薄膜５の代わりに、ＰＳＧの薄膜を用いてもまったく支
障ない。Here, the silicon dioxide thin film 3 does not need to be formed by atmospheric pressure CVD, and low pressure CVD 1 can also be used. There is no problem at all even if a thin film is used.
以上説明し念ように、本発明は、全面上限なく被覆する
性質を持ったＣＶＤ のリンを含まない二酸化ケイ素金
先ず全面につけて、第二層のシリカフィルムに含まれる
リンによる耐湿性の低下金未然に防止し、第二層のシリ
カフィルムによって全体の平坦化が出来、必要に応じて
その上から堆積する層の均一な被覆を可能にして弱点部
を解消することにより１表面保護機能の程度を格段に向
上できる効果がある。As explained above, the present invention is to first apply CVD phosphorus-free silicon dioxide gold to the entire surface, which has the property of covering the entire surface without any upper limit, and to reduce moisture resistance due to phosphorus contained in the second layer of silica film. The second layer of silica film can flatten the entire surface, and if necessary, it can be coated evenly with a layer deposited on top of it to eliminate weak points, thereby increasing the degree of surface protection function. It has the effect of significantly improving
第１図は本発明の一実施例を示す完成し几素子の表面部
の断面図、第２図は従来のカバー構造上水す断面図であ
る。
１・・・・・・層間絶縁膜の表面％２．６・・・・・・
アルミ配線、３・・・・・・二酸化ケイ素の薄膜、４・
・・・・・シリカフィルム、５・・・・・・窒化シリコ
ンの薄膜、７・・・・・・ＰＳＧ膜。
代理人 弁理士 内 原 晋
’ｆ−ｚ回FIG. 1 is a cross-sectional view of the surface of a completed device showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional cover structure. 1... Surface % of interlayer insulating film 2.6...
Aluminum wiring, 3...Silicon dioxide thin film, 4.
... Silica film, 5 ... Silicon nitride thin film, 7 ... PSG film. Agent Patent Attorney Susumu Uchihara 'f-z times
Claims (1)
層の薄膜と、その凹凸部を充填するシリカフィルムの第
２層とを含む表面保護膜を有することを特徴とする半導
体集積回路装置。A first layer of silicon dioxide deposited by vapor deposition.
1. A semiconductor integrated circuit device comprising a surface protective film including a thin film layer and a second layer of silica film filling the uneven portions of the surface protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16887685A JPS6230337A (en) | 1985-07-31 | 1985-07-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16887685A JPS6230337A (en) | 1985-07-31 | 1985-07-31 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6230337A true JPS6230337A (en) | 1987-02-09 |
Family
ID=15876197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16887685A Pending JPS6230337A (en) | 1985-07-31 | 1985-07-31 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6230337A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5183772A (en) * | 1989-05-10 | 1993-02-02 | Samsung Electronics Co., Ltd. | Manufacturing method for a DRAM cell |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5290276A (en) * | 1976-01-26 | 1977-07-29 | Oki Electric Ind Co Ltd | Production of semiconductor device |
-
1985
- 1985-07-31 JP JP16887685A patent/JPS6230337A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5290276A (en) * | 1976-01-26 | 1977-07-29 | Oki Electric Ind Co Ltd | Production of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5183772A (en) * | 1989-05-10 | 1993-02-02 | Samsung Electronics Co., Ltd. | Manufacturing method for a DRAM cell |
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