JPS6229952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tuning display device used in a television receiver, and more particularly to a device for displaying an image representing a tuning state on a cathode ray tube.

In many television receivers, the tuning state of the tuner is expressed by a change in the width of a video band displayed on a cathode ray tube. However,
Conventionally, such devices have had the disadvantage that although the tuning state of any channel is displayed, it is not displayed which channel it is, making it difficult to identify the channel. In particular, instead of using a conventional rotary switching tuner, a binary counter, binary memory, and D-A converter are used to change the tuning voltage simply by switching the binary counter's count up and count down. The disadvantage of the preparation was that it was difficult to identify the channel.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a device that can easily display both the tuning state and the current channel, that is, the frequency, thereby facilitating the tuning operation. It is something to do.

EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment thereof. In the figure, 1 is a tuner, 2 is a VIF circuit, 3 is a video detection circuit, 4 is a video amplification circuit, 5 is a chroma circuit, and 6 is a cathode ray tube, and illustration of other image receiving circuits is omitted. The tuner 1 includes an RF amplifier circuit 7, a mixing circuit 8, and a voltage-controlled local oscillation circuit 9, and also includes a binary counter as a means for generating a tuning voltage to be applied to the local oscillation circuit 9, etc. 1
0, a memory 11, and a D/A converter 12. The binary counter 10 is for generating a digitized signal of the tuning voltage, and when the count-up switch 10u or the count-down switch 10d is operated, the clock pulses are counted and the digitized signal is changed. . During this tuning adjustment, the digitized signal output from the binary counter 10 is applied as is or via the memory 11 to the D/A converter 12, where it is converted into an analog tuning voltage and applied to the local oscillation circuit 9, etc. . Therefore, when the switches 10u and 10d are operated, the tuning voltage is gradually changed, and the tuning frequency is gradually adjusted. When the desired tuning condition is achieved, the digitized signal at that time is stored at a predetermined address in the memory 11. The addresses are switched by channel switching switches 11a, 11b, . . . . In this way, 2
The digital signal from the counter 10 is applied to a tuning circuit 13a tuned to the VIF center frequency, and its output is connected to a diode 13b and a capacitor 13.
Detection and smoothing is performed at c to create a detection voltage whose magnitude changes according to the frequency shift. This detection voltage is applied to the base of transistor 13d.
On the other hand, a horizontal periodic sawtooth wave voltage is applied from the terminal 13e, and is coupled to the collector and emitter of the transistor 13d via a clamp circuit 13f and further via diodes 13g and 13h. Therefore, in this circuit, a sawtooth wave voltage with a horizontal period is clipped, and an output is taken out in which the clip levels above and below are controlled by the detection voltage in the tuned state.
Further, the voltage is differentiated by the capacitor 13i and the resistor 13j, and a tuning display pulse is created in the horizontal period, which is located in the center of the horizontal period and whose pulse width becomes narrower as the detected voltage is larger. After the digitized signal is stored in the memory 11, when a channel is designated by operating the switches 11a, 11b, etc., the digitized signal at the address of that channel is read out from the memory 11, and the D/ Tuning is performed by converting the voltage into a tuning voltage in the A converter 12 and applying it to the local oscillation circuit 9 and the like.

Next, a description will be given of a tuning state and frequency display circuit section applied to such a receiver.

First, reference numeral 13 is a tuning display pulse generation circuit that generates a tuning display pulse to indicate the tuning state, and detects the frequency of the VIF signal taken out from the VIF circuit 2, that is, the output signal of tuner 1, and
Generates a tuning display pulse with a horizontal or vertical period whose pulse width changes depending on the deviation from the VIF center frequency (carrier frequency). In this embodiment, the tuning display pulse is waveform-shaped and amplified by the transistor 13k and output.

On the other hand, 14 is a frequency display pulse generation circuit that generates a frequency display pulse with a vertical period or horizontal period for displaying the tuned frequency in the tuner 1, and is supplied from the D/A converter 12 to the local oscillation circuit 9, etc. It detects the tuning voltage and generates a pulse whose pulse width changes depending on the magnitude of the tuning voltage. In this embodiment, a comparison circuit consisting of transistors 14a and 14b connected as a differential amplifier is used, and a tuning voltage taken out from the D/A converter 12 is applied to the base of the transistor 14a, and is also supplied from the terminal 14c. The sawtooth wave voltage with the vertical period is applied to the base of the transistor 14b, the two are compared, and as the comparison output, a frequency display pulse whose pulse width is wider as the tuning voltage is larger is created with the vertical period. .

Then, these tuning display pulses and frequency display pulses are applied to a display pulse generation circuit 15, where a substantial AND output of the two is created and a display pulse is generated. That is, a tuning display pulse is applied to the base of one transistor 15a of the transistors 15a and 15b connected in series, and a frequency display pulse is applied to the base of the other transistor 15b. An indication pulse is generated only when both pulses are present.

Therefore, this display pulse is sent to one of the color output circuits in the chroma circuit 5 or to the video amplification circuit 4.
By applying this voltage, a display image 16 is projected on the screen of the cathode ray tube 6 as shown in FIG. In this image 16, the width W in the horizontal direction is determined by the pulse width of the tuning display pulse,
The vertical length l is determined by the pulse width of the frequency display pulse.

Therefore, by adjusting the tuning frequency by operating the switches 10u and 10d while viewing such an image 16, the operator can first determine the tuning frequency, that is, the channel, by looking at the length l. Furthermore, by looking at the width W, it is possible to know how much the channel is deviated from the center frequency, and by knowing both, it is possible to easily make accurate adjustments.

In the above embodiment, the display pulse generation circuit 15 was provided independently, but the video amplification circuit 4
Alternatively, it goes without saying that the AND signal may be created by controlled elements in the chroma circuit 5.

As detailed above, in the present invention, both the tuning state and the frequency are displayed on the cathode ray tube using one display image, so the operator can know both the tuning state and the frequency at a glance when making adjustments. This allows easy and accurate adjustment.

Furthermore, in the present invention, since both the width and length of the image that displays the tuning state and frequency are continuously changed, it is easy to see which direction the tuning is being made with respect to the optimal tuning state during adjustment. This can greatly improve operability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a tuning display device according to an embodiment of the present invention, and FIG. 2 is a front view showing a display mode of the device. 1... Tuner, 2... VIF circuit, 3... Video detection circuit, 4... Video amplification circuit, 5... Chroma circuit, 6... Cathode ray tube, 7... RF amplifier circuit, 8...
... Mixing circuit, 9 ... Local oscillation circuit, 10 ... Binary counter, 11 ... Memory, 12 ... D/A converter, 13 ... Tuning display pulse generation circuit, 1
4... Pulse generation circuit for frequency display, 15... Pulse generation circuit for display, 16... Display image.

Claims (1)

[Claims] 1. A tuner whose tuning frequency is controlled by a tuning voltage, and a tuner that detects the frequency of the IF output signal of this tuner and continuously changes the pulse width according to the deviation from the IF center frequency. A tuning display pulse generation circuit that generates a tuning display pulse with a changing horizontal period or vertical period, and a frequency display circuit with a vertical synchronization or horizontal period whose pulse width changes continuously according to the magnitude of the tuning voltage. comprising a frequency display pulse generation circuit that generates a pulse, and a display pulse generation circuit that generates a display pulse by creating a substantial AND output of the tuning display pulse and the frequency display pulse, A tuned display device characterized in that the display pulses are used to display on a cathode ray tube an image whose width and length continuously change depending on the tuning state and frequency. 2. A binary counter for generating a digitized signal of the tuning voltage as means for generating a tuning voltage, and a memory for storing this digitized signal;
2. The tuning display device according to claim 1, further comprising a D/A converter which converts said digitized signal into a D/A converter to obtain said tuning voltage.