JPS62297154A - Drive circuit of long size electronic apparatus - Google Patents

Abstract

PURPOSE:To decrease the number of connecting signal wires in split drive and besides, and to enable the control of the number of functional elements of drive heating units or the like, by using the shift register for transfer of data also as the shift register for transfer of pulse conduction signal. CONSTITUTION:In addition to the output Q of pulse conduction control signal SB and a latch 4 as the input to a gate circuit 10 connecting a heating unit to the drive transistor to be driven by pulse conduction, the output Q of a shift register 2 is connected as the third input. Then, the recording data of one line content is inputted to a shift register 2 and parallel transmitted to the latch 4. Thereafter, the pulse of a time width equivalent to the conducted pulse is transferred in the shift register as data, and the AND of the output of latch 4 and the output of shift register 2 is outputted to a drive transistor by making a pulse conduction control signal SB to be of active side. Then, the number of the bits simultaneously heating can be regulated and the number of the connecting signal wires of the pulse conducting control signal therefor can be decreased.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Technical Field) The present invention relates to a drive circuit for a long electronic device such as a thermal head, an LED array, or a fluorescent tube array.

(Prior Art) A driving circuit for a thermal head will be described as an example.

FIG. 8 shows a driving circuit for one bit of the heating element of the thermal head. Usually, 32 bits or 64 bits are integrated into one integrated circuit device for a driver circuit. FIG. 9 shows a timing chart in the drive circuit of FIG. 8.

2 is a shift register, which transfers the recording data DI in synchronization with the clock CK. 4 is a latch, and the output Q of the shift register 2 is input to its input. In addition, the load signal LD is applied to the gate input G of the latch 4.
is entered. 6 is a gate circuit, to which the energization control signal 5B (SBI to 5B8) is input as one input, and the output Q of the latch 4 is input as the other input. The output of the gate circuit 6 is connected to a drive transistor that drives the energization of the heating element.

After the recording data DI for the total number of heating elements is input to the shift register 2, when the load signal LD is input, the latch 4 holds the recording data DI.When the energization control signal SB is turned on, recording is performed only during the ON period. Data is input to the drive transistor to energize the heating element.

The energization control signal SB is wired so that one energization control signal SB is supplied to each block, with a plurality of drive circuit integrated circuit devices as one block, in order to drive the heating elements in a divided manner. FIG. 1O shows, as an example, the connections between the drive circuit integrated circuit devices 8-1 to 8-32 and the energization control signals 5BI-3B8. In this way, in the conventional drive circuit, the heating element of the thermal head is energized by the energization control signal S.
A plurality of B are prepared, and divisional driving is performed by sequentially turning on each energization control signal.

However, according to such a drive circuit, the number of energization control signals SB required is equal to the number of divisions, so signal connections between the thermal head and the external circuit are required accordingly.

If the number of divisions is increased, there is a problem that the number of energization control signals SB increases.

Furthermore, the maximum number of heat generating elements that generate heat at the same time is fixed by the connection of the energization control signal SB.

In order to reduce the number of signal lines for energization control signals, a system in which a device that converts energization control signals from serial to parallel, such as a combination of a counter and a decoder, or a shift register, is mounted separately from the integrated circuit device for the drive circuit. However, such a system has the problem of requiring an extra integrated circuit device to be implemented.

(Objective) The present invention makes it possible to limit the number of bits that generate heat at the same time in order to reduce the capacity of a power supply for driving a functional element of a long electronic component, such as a heating element in a thermal head, by tJz. The purpose of this invention is to reduce the number of connection signal lines for energization control signals compared to conventional ones.

(Configuration) In the conventional drive circuit, the gate circuit 6 has only two inputs: the latch output Q and the energization control signal SB, but in the present invention, in addition to those two inputs, the output of the shift register is also input. The third input is input to the gate circuit 6, one line of recording data is input to the shift register 2, and after being transferred in parallel to the latch 4, a pulse with a time width corresponding to the energization pulse is input into the shift register 2 as data. is transferred, the energization control signal SB is activated, and the AND of the output of the latch 4 and the output of the shift register 2 is output to the drive transistor.

Examples will be specifically described below.

FIG. 1 shows an embodiment in which the present invention is applied to a thermal head, as a drive circuit for one bit of a heating element.

The configurations of the shift register 2 and latch 4 are similar to the conventional one shown in FIG.

In this embodiment, in addition to the energization control signal SB and the output Q of the latch 4, the shift register 2
It differs from the one shown in FIG. 8 in that the output Q of is connected as the third input.

In this embodiment, as shown in FIG.
32 in common.

FIG. 3 shows a timing chart of the operation of this embodiment.

The steps up to the point where the recording data DIl is transferred by the recording data transfer lock CK1 and the load signal LD is input are the same as the conventional drive circuit shown in FIG.

Thereafter, the energization control signal SB is activated (high level in this embodiment), and a pulse corresponding to the energization time of the heating element is input as the data DI to the shift register 2 as the energization pulse signal DI2. Transfer with transfer lock CK2. As a result, pulses similar to the conventional energization control signal SB are sequentially input to the gate circuit 10 of each heating element.

Figure 4 shows the output of each bit of shift register 2.
A clock CK? sets the period (time T) in which the input signal DI2 of the shift register 2 is at a high level as the energization time of the heating element. When input, energization pulse signal DI for 1 hour T)
In the embodiment shown in FIG. 4, in which T/l is sequentially output and input to the gate circuit 10, T/l=4, so the number of bits that are energized at the same time is 4, but by changing this ratio, The number of bits energized can be freely changed. For example, in a thermal head with a total number of bits of 2048, if T/1=256, the actual number of bits is 2048/
256=8 corresponds to 8 divisions, and T/1=512 corresponds to 4 divisions. In that case, even if the number of divisions is changed, the connection between the energization control signal SB and the driving circuit integrated circuit device is as shown in FIG. 2, and there is no need to change this connection.

When printing is performed using a thermal head, the ratio of the black printed area to the white background area varies.

In the conventional drive circuit as shown in FIG. 8, recording requires a certain amount of time regardless of the recording data. Also.

The power source needs to have a current capacity necessary when all the heating elements in one block of the energization control signal SB generate heat.

If you want to set a limit on the number of bits that generate heat at the same time, you can control the number of black dots in the recorded data and use that to decide where in the divided blocks to apply electricity. can. However, such control has the problem of requiring extra control outside the thermal head, that is, on the user side of the thermal head.

Therefore, in addition to the embodiment shown in FIG. 1, FIG. 5 shows two types of transfer locks C as transfer locks for the energization pulse signal DI2.
An embodiment will be described in which KA and CKB are prepared and a circuit is added that determines which transfer lock is selected for each bit based on the content of data in latch 4.

When compared with the drive circuit in Figure 1, the AND circuit is 14.16
and an OR circuit 18 are added, and one input of the AND circuit 14 is a lock C that transfers the energization pulse signal of black printing data.
The KA line is connected, and the output Q of the latch 4 is connected to the other input. One input of the AND circuit 16 is a lock CKB that transfers the energizing pulse signal for internal printing data.
line is connected, and the other input is the output Q of latch 4.
is connected. The outputs of the AND circuits 14 and 16 are connected as two inputs of the OR circuit 18, and the output of the OR circuit 18 is connected to the clock input terminal C of the shift register 2.
connected to K.

Next, the operation of this embodiment will be explained using the timing chart of FIG.

The process up to transferring and latching the recorded data is the same as the conventional one. Q1 to Q5 are outputs of the shift register 2. It is assumed that the first bit latch 4 holds black data, the second bit latch 4 holds white data, and the following data is black, white, and white. An energization pulse signal DI2 for a time T for energizing the heating element is input to the input of the shift register 2. Let the periods of clocks CKA and CKB be tl and t:, respectively.

In the example of FIG. 6, tl=T/3, t:=T/
It is 12.

When the data in latch 4 is a black bit, output Q becomes high level and clock CKA is selected.

When the data in latch 4 is a white bit, output Q becomes high level and clock CKB is selected.

Therefore, if the data in the latch 4 is a black bit, the energizing pulse signal OT2 is transferred at time 11, and if the data in the latch is white, the energizing pulse signal DI2 is transferred at time t2.
is transferred. Also, the number of bits that generate heat at the same time is T/l
It is limited by +=3.

For example, assume that the time T required for heat generation is 1 millisecond, the period t1 of the clock CKA is 1/40 millisecond, and the period t2 of the clock CKB is 1 microsecond.

Under these conditions, the black rate is 1 on A4 size (216mm x 296m)
When printing 5% (equivalent to a normal text document) at 8 dots/mm, 216 x 8 x 296 x 8 = 40
The total number of dots is 91904 dots, and the number of heating dots is 409.
1904 X O,15=613786 dots.

Therefore, the recording time is (1/40) milliseconds x 613
786 + 1 microsecond x (4091904-61
3786)=18.8 seconds.

If the same printing is done using the conventional method with 8 divisions,
296 x g x g milliseconds = 18.9 seconds.

On the other hand, assuming that the required power supply is 30 mA per dot, the number of dots that can generate heat at the same time in the conventional drive circuit is 216 x 8 ÷ 8 = 216 dots.
30m A x 216 = 6.48A. On the other hand, in this example of the present embodiment, there is a possibility that 40 dots generate heat at the same time, so 30 m A x 40 dots
= 1.2A, which saves power.

FIG. 7 shows yet another embodiment. Compared to the embodiment shown in FIG. 5, an OR circuit 20 is inserted between the output Q of the shift register 2 and the input of the AND gate circuit 10, and the mode signal MOD is input to the other input of the OR circuit 20. They differ in some respects.

In the embodiment shown in FIG. 7, by setting the mode signal MOD to a high level, it is possible to use the circuit in exactly the same way as the conventional drive circuit shown in FIG. That is, during printing, the next print data is input to the shift register 2 and transferred.

According to the embodiments shown in FIGS. 5 and 7, the number of dots that generate heat at the same time is constant regardless of the recorded data, so density unevenness due to black percentage is less likely to occur. Furthermore, the capacity of the power supply can be reduced without reducing the recording speed.

Although the above-described embodiments are all related to thermal head drive circuits, the present invention is not limited to thermal heads, but can also be applied to drive circuits for LED arrays, fluorescent display tubes, and the like.

(Effects) According to the present invention, the shift register for data transfer also serves as a shift register for energizing pulse signal transfer, so the number of connected signal lines during split driving can be reduced.

The number of functional elements such as heating elements that are driven simultaneously can be limited, and the number can be freely set.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a schematic diagram showing the connection relationship between the integrated circuit device for the drive circuit and the energization control signal in the same embodiment, and FIG. 3 is the operation in the same embodiment. FIG. 4 is an timing chart showing details of the transfer state of the energizing pulse signal, FIG. 7 is a circuit diagram showing still another embodiment of the present invention, and FIG. 8 is a drive of a conventional thermal head. FIG. 9 is a timing chart showing the operation of the conventional drive circuit, and FIG. 1O is a schematic diagram showing the connection state between the integrated circuit device for the drive circuit and the energization control signal in the conventional example. 2...Shift register, 4...Latch, 10...Gate circuit.

Claims (1)

[Claims] (1) A shift register that transfers input data, a latch that inputs the data transferred by this shift register in parallel, and a driving transistor that drives a functional element;
A drive circuit comprising a gate circuit that is operated by an energization control signal and operates the driving transistor according to data of the latch, wherein the gate circuit has three inputs: a shift register output, a latch output, and an energization control signal; After inputting one line of recording data to the shift register and transferring it in parallel to the latch, a pulse with a time width corresponding to the energization pulse is transferred as data in the shift register, and the energization control signal is set to the active side. A drive circuit for a long electronic device, characterized in that a logical product of a latch output and a shift register output is output to a drive transistor.