JPS62296240A - Error processing system - Google Patents

Abstract

PURPOSE:To prevent the block separation generated due to an error occurring continuously in the time by stopping the stepping of an error counter in a constant time from the next cycle until the processing of the instruction is interrupted when the error occurs at a RAM included in a certain block. CONSTITUTION:A gate 11 obtains the AND of an error signal and the output of a timer 10. Synchronizing with the error signal, the timer 10 is started, the logic of the signal and the error signal is obtained and during the starting of the timer 10, the input of the error signal to an error counter 4 is prohibited. Thus, when the error generated at the block is a temporary soft error, the start of the processing to the error generated at the block is avoided and the separation of the block can be prevented.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] When an error occurs in the RAM included in a block, the error occurs within a certain period of time from the next cycle until instruction processing is interrupted. Configure the counter to stop incrementing,
To prevent block separation caused by errors occurring continuously within the time period.

[Industrial application field]

The present invention increments an error counter every time an error occurs in the RAM, and increments the error counter when an error occurs during count amplification.
The present invention relates to an error processing method that improves the incrementing manner of an error counter when separating a block containing a block.

In an information processing device that uses a pipeline method as an instruction processing method, when an error occurs in the RAM, the instruction processing is interrupted and the contents of the RAM of the block where the error occurred are cleared.

However, it takes at least several machine cycles before this clearing begins, during which time processing of subsequent instructions flows to the vibe line. Generally, in a sequence of consecutive instructions, RA
The same part of M may be accessed. In this case, R
If there is an error in AM0, the error will occur continuously for a number of machine cycles until instruction processing is interrupted. Then, the value of the error counter increases all at once, causing the inconvenience that the block including the R'AM in which the error has occurred is separated.

Therefore, if a continuous error occurs as described above,
Due to this, there is a demand for a proposal for a circuit that prevents the error counter from incrementing.

[Conventional technology]

As shown in FIG.
ION LOOKASIDE BIIFFER)? A TLB primary block 2 connected to a address register 1 is checked for error occurrence by a parity check circuit 3, and an error counter 4 is incremented every time an error occurs. As shown in FIG. 5, when the error counter 4 counts a preset count value n (for example, 4), a TLB primary block delete signal is generated from the DELETE register 5,
Separate TLB primary block 2.

Incidentally, when processing each instruction, the instruction address and operand address are outputted to the address conversion section for conversion from a logical address to an absolute address by reading the TLB. In FIG. 3, the TLB is composed of a primary block 2 and an alternate block 6, which have the same function, and the functional parts are duplicated. Although not shown, similar automatic disconnection means is provided.

[Problem that the invention seeks to solve]

In this conventional circuit, the count up of the error counter 4 always occurs every time an error occurs. The TLB block where the error occurred will be separated. For this reason, even if the RAM error is a temporary soft error, blocks are separated, making it impossible to use the RAM efficiently.

The present invention was created in view of the above problem, and it provides a solution to errors that occur continuously until an instruction is executed due to a memory error. The purpose is to provide an error handling method that can avoid the occurrence of errors.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the error handling method of the present invention.

In the figure, numeral 10 is a timer that is activated for a certain period of time upon occurrence of an error, and numeral 11 is a gate that takes the AND of the error signal and the output of timer 10.

[For production]

The timer 10 is activated in synchronization with the error signal (F)+L, and the logic between that signal and the error signal is determined, and input of the error signal to the error counter 4 is prohibited while the timer 10 is activated.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which the gate 11 uses a circuit consisting of an inverter 12 and an AND gate 13.

As shown in FIG. 3, the timer 10 is activated in synchronization with the generation of the error signal (TLB-ELR) output from the parity check circuit 3. The timer 10 is O<T<
The operating time is set within a range of 5τ (here, the error interval). The output of the timer 10 is inverted by an inverter 12. Therefore, if the timer 10 is in operation and its output is 1 level, the output of the inverter 12 will be at the I5 level. The output of the inverter 12 and the output of the parity check circuit 3 are each applied to an AND gate 1-13, where a logic is determined. AND gate 13 is
When both people's strength is at H level at the same time, that is, timer 10
A signal is applied to the error counter 4 only when an error signal is output from the parity check ff-/recircuit 3 after the completion of the operation. Therefore, as shown in FIG. 3, even if an error signal is output from the parity check circuit 3 within the timer setting time, the AND condition is not satisfied and the error signal generated during that time is not counted by the counter 4. .

Note that when processing each instruction, the instruction address and operand address are outputted to the address conversion section for conversion from a logical address to an absolute address by reading the TLB. In FIG. 2, the TLB is composed of a primary block 2 and an alternate block 6, which have the same function, and their functions are duplicated. It is configured so that when an error occurs, one side can be disconnected and instruction processing can continue.

[Results of invention]

As described above, according to the present invention, when an error that occurs in a block is a temporary soft error, it is possible to avoid taking action for the error that occurs in that block and prevent the block from being separated. Can be done.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the error processing method of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a time chart in the present invention, and Fig. 4 is an explanatory diagram of a conventional circuit. , FIG. 5 is a time chart in the conventional circuit. In FIG. 2, 3 is a parity check circuit, 4 is an error counter, 10 is a timer, 12 is an inverter, and 13 is an AND gate. Patent applicant: Fujitsu Ltd.-5, Principle of the present invention 707 Figure 1 Figure 7 Block diagram of the explanation Figure 2 Time chart of conventional method 4 Figure 5 1-@---←- −→−−−←−−←−−1−−−÷−
−→−−−Time chart of tote register register Honda circuit Fuparock diagram of party rice circuit Fig. 4

Claims (1)

[Claims] Data processing resources are divided into blocks, errors in memory within one block are detected by an error check circuit (3), and the number of times the error occurs is counted by an error counter (4), and the count value is a set value. In a system configured with a means for handling an error in the error block when the error occurs, the system operates for a preset time in synchronization with the error signal output from the error check circuit (3). A timer (10) and a gate circuit (11) that gates the output of the error check circuit (3) upon completion of the operation of the timer (10) are provided, and the error counter responds to the output of the gate circuit (11). (4) An error processing method characterized in that the processing means is activated by a signal outputted from the block, and processing is performed for the error in the error-occurring block.