JPS62293730A - Manufacture of inter-substrate connector - Google Patents

Abstract

PURPOSE:To prevent the penetration of solder by melting by forming a multilayer metallic layer, using Al with no pin hole as a mask even in low- temperature evaporation. CONSTITUTION:When Al is employed as a mask material, Cu(l'') in a lower surface is etched by an ammonium persulfate aqueous solution, etc., using patterns o' and o'' slightly larger than an opening (p) acquired by laminating filmy resists on an upper surface and the lower surface and developing the filmy resists as masks, the filmy resists are peeled by employing acetone, etc., the filmy resists o''' are laminated again, and Cu(l') in the upper surface is etched by the ammonium persulfate aqueous solution, etc. Al (a) is etched by hydrochloric acid, etc., and the filmy resist o''' on the lower surface is peeled by employing acetone, etc., thus shaping multilayer metallic layers. A fine solder sphere is arranged to the Cu(l) section of the upper surface through the mask, and heated and melted, and cooled and fixed, thus forming a fundamental structure to which a solder bump is fastened.

Description

3. Detailed description of the invention Technical field to which the invention pertains The present invention relates to terminal connection technology, and in particular to a method of manufacturing inter-board connection terminals.

BACKGROUND OF THE INVENTION An inter-board connection terminal (Showa Indo Patent Application No. 156621) has been proposed as a terminal connection method between a large chip and a wiring board. FIG. 5 is a diagram showing the above embodiment, in which a is a chip, b is an electrical type, C is a wiring board, d is a terminal portion, e is a solder bump, and l.

E' and II' are metal layers such as Cu that are wettable with solder, m is a diffusion prevention layer such as Ti that is not wettable with solder and is sandwiched between metal layers l and E'; n is a heat-resistant resin film such as polyimide. A conventional manufacturing method for the inter-board connector shown in FIG. 5 will be explained with reference to FIG. As shown in Figure 6(a), 12.5 to 25 μm
Cu (approximately 5 μm) and Ti (approximately 0
．． 2-1 μm) ICu (about 5 μm), Ti (about 0.5-1 μm)
1 pm) is continuously deposited on f@l'm -1-m', and Cu (1') is deposited on the lower surface. Next, the 6th
As shown in Figure (b), a film resist with a thickness of about 50 μm is laminated on both sides, and this is sandwiched between two masks that have been aligned in advance, and both sides are exposed.
Using trichloroethane etc., film resist 0
Develop it to obtain the desired pattern. Next, as shown in FIG. 6(e), C:u (1') on the lower surface is etched with an aqueous ammonium persulfate solution that is selective to Ti.

Next, as shown in FIG. 6(d), as a film-like mask on the upper surface, Ti(m') is etched with a hydrofluoric acid aqueous solution that is selective to Cu, and an ammonium persulfate aqueous solution is etched. Then, the Ti (m) is etched using a hydrofluoric acid aqueous solution or the like. Next, as shown in FIG. 6(e), after peeling off the film resist 0 using acetone or the like, the polyimide film N as a Cu(J') t-mask on the lower surface is etched using a hydrazine aqueous solution or the like. , obtain the aperture p. Next, as shown in FIG. 6(f), film resists are laminated and developed on the upper and lower surfaces to obtain battens 0' and 0' with slightly larger openings. next,
Using these film resists 0' and 0' as masks, the Cu(1') on the lower surface was etched with ammonium persulfate aqueous solution, etc., and then the film resist was peeled off using acetone etc., as shown in Fig. 6(g). As shown, form a film again, laminate the resist o''', and remove the C on the upper surface.
Etch u(/') with an aqueous ammonium persulfate solution. Next, as shown in FIG. 6(h), after etching with a hydrofluoric acid aqueous solution or the like, the film-like film on the lower surface is etched with acetone or the like to form a multilayer metal layer. are doing.

Generally, when metal is vacuum-deposited, a dense metal film without pinholes can be obtained by heating the sample to a high temperature. During the above manufacturing process, when continuously vapor depositing Cu-Ti-Cu-Ti on a polyimide film, if it is heated at high temperature, the thin polyimide film serving as the substrate will be deformed due to thermal expansion and a metal film will be formed. This makes it difficult to form battens in subsequent steps. Therefore, in this manufacturing method, it is necessary to form the metal layer at a low temperature without heating the sample in order to prevent the polyimide film from deforming due to thermal expansion. However, when Ti is formed by low-temperature vapor deposition, the film becomes porous. For this reason, the sixth
As shown in figure (g), when chemically etching Cu (A”) on the upper surface using Ti (rrr) as a mask, T
The Cu(1) layer under the i(m') mask is also etched, resulting in many pinholes reaching the Ti(m) layer sandwiched in between. In this state, as shown in FIG. 6(h), when the top layer of Ti(m') is removed by etching with a hydrofluoric acid aqueous solution, the Ti(m') exposed in the pinholes generated is removed.
(m) layer is also etched, sandwiching Ti (m)
Many pinholes (h) are also generated in the layer.

Therefore, as shown in FIG. 7, when the solder ball is melted, there is a problem in that the solder partially penetrates through the pinhole portion and becomes integrated.

OBJECTS OF THE INVENTION An object of the present invention is to provide a method for manufacturing a multilayer metal layer that completely prevents penetration of solder due to melting in the manufacturing process of connection terminals for multi-stage solder bumps.

Structure of the Invention Characteristics of the Invention and Differences from the Conventional Technology In the conventional technology, 1
Since a multilayer metal layer is formed, there are many pinholes in the multilayer metal layer. However, as in the present invention,
A good multilayer metal layer without pinholes can be formed by using a method of forming a multilayer metal layer using AJ as a mask, which has no pinholes even at low temperature evaporation, or a method of forming a multilayer metal layer by plating without using a mask. It differs from conventional technology in that it can be done.

Embodiment FIG. 1 shows a first embodiment of the manufacturability of the present invention in which multilayer metal layers are formed at low temperatures. Using Figure 1,
A process for manufacturing an inter-board connection terminal when AJ is used as a mask material will be described. As shown in Figure 1(a),
Using a polyimide film n of approximately 12.5 to 25 μm as a base material, Cu (approximately 5
pm) *Ti (approximately 0.2-1 μm).

Cu (approximately 5 μm) = °C; ≠#kej1ko→-, A1. (approximately 0.5 to 17 zm): 72 is continuously deposited on this mold 1'm-1-a, and ICu (approximately 2 .mu.m) l'f is deposited on the lower surface. Next, as shown in FIG. 1(b), a thickness of 50 mm is applied to both sides.
A film resist (dry film) of about 100 pm is laminated, sandwiched between two masks that have been aligned in advance, exposed on both sides, and a developer such as trichloroethane is used to create a film resist 0. Develop the
Get the desired bang. Next, as shown in Figure 1(c),
Etching is performed using a filtered aqueous ammonium sulfate solution that is selective to Cu (l') t kl and Ti on the lower surface. Next, as shown in FIG. 1(d), as a film-like mask on the upper surface, Al(&) is etched with hydrochloric acid that is selective to Cu, and Cu(&) is etched with an aqueous ammonium persulfate solution. 1) is etched, and finally 'pi(m) is etched with a hydrofluoric acid aqueous solution having selectivity to Al and Cu.

Next, as shown in FIG. 1(e), after peeling off the film resist 0 using acetone or the like, the Cu(
Using polyimide film nf as a mask, etching is performed with an aqueous hydrazine solution to obtain an opening p. Then the first
As shown in Figure (f), a film-like resist is completely laminated and developed on the upper and lower surfaces to obtain battens 0' and 0' with slightly larger openings p. Next, as this film resist 0' and a hot mask, Cu on the lower surface is
After etching (J') with an aqueous ammonium persulfate solution or the like, the film resist is peeled off using acetone or the like, and the film resist is formed again as shown in FIG. 1(g). ' is laminated, and Cu(l') on the upper surface is etched with an aqueous ammonium persulfate solution. Then the first
As shown in Figure (h), after AJ(a)i etching with hydrochloric acid or the like, the film-like resist Q'' on the lower surface is peeled off using acetone or the like to form a multilayer metal layer. Micro solder balls are placed on the Cu (J) part of the surface through a mask, heated and melted, and then cooled and fixed to form a basic structure with fixed solder bumps, as shown in Figure 1 (i). .

It should be noted that the manufacturing method is not limited to the first embodiment shown here, and it is possible to change the manufacturing method within the scope of the claims of the present invention. For example, AII alloys such as AISi, AlCu, etc. containing a small amount of other substances can also be used as the mask material.

Furthermore, as a mask material, C
r etc. can also be used.

FIG. 2 shows a second embodiment of the manufacturability of the present invention in which multilayer metal layers are formed at low temperatures.

Hereinafter, referring to FIG. 2, the entire process of forming a multilayer metal layer by electroless plating or the like will be explained. As shown in Figure 2(a), a 12.5-25 μm 8 degree polyimide film n
is used as a base material, and the upper surface is covered with Cu (approximately 5 μm)! , Cu (approximately 2 μm) f is deposited on the lower surface by vapor deposition, sputtering, or by pasting a Cu foil with an adhesive that cures at room temperature. Next, as shown in Figure 2(b), a film resist (dry film) with a thickness of about 50 μm is laminated on both sides, the lower surface is exposed, and the film resist 0 is developed using trichloroethane or the like. and get the desired bang.

Next, as shown in Figure 2(e), Cu(J') on the lower surface
'? Etch with an aqueous ammonium persulfate solution.

Next, as shown in FIG. 2(d), after forming a film using acetone or the like and peeling off the mask, a polyimide film (Curl') on the lower surface was used as a mask.
g Etching with hydrazine aqueous solution etc. to open the opening p'lt.
obtain. Next, as shown in Figure 2 (,), a film resist is laminated on the upper surface, and a Cr metal layer m5 that is not wettable with solder is electrolytically plated in an aqueous solution such as chromic acid to form the opening p. After forming the solder, a Cu film having a thickness of about 5 μm is formed by electroplating q' such as Cu, which is wettable to solder, in an aqueous solution such as copper sulfate. Next, as shown in FIG. 2(f), a film-like resist (about 50 pm to 100 μm thick) is applied to both the upper and lower surfaces.
A dry film) is laminated and developed to obtain resist patterns q and q' having holes slightly larger than the opening p. Next, using the film resists q and q' as masks, a solder layer (5
0 to 100 μm)@le' is formed by electrolytic plating in an aqueous solution or the like. Next, as shown in FIG. 2(h)K, a film is formed using acetone or the like, and after a distance of 1° from a distance of 1°, a solder layer@le' layer is formed as shown in FIG. 2(i). As a mask, Cu (
J) and Cu(q') on the lower surface are etched with an aqueous ammonium persulfate solution. Next, in this state, the solder is melted through an electric furnace to form solder bumps to form terminal connectors (FIG. 2 (j)).

It should be noted that the manufacturing method is not limited to the second embodiment shown here, and it is possible to change the manufacturing method within the scope of the claims of the present invention. For example, when forming a solder layer, it is also possible to plate Pb and Sn separately.

Next, the reason for adopting such a manufacturing method will be explained.

When patterning a multilayer metal layer of % Cu TI Cu in an inter-substrate connector (Showa ω 2004 patent application No. 156621), when Ti is used as a mask material, the etching solution is It penetrates into the Ti of the mask, etching the multilayer metal layer and creating pinholes as shown in FIG. Note that although the Ti sandwiched in the middle is also porous, penetration of solder can be prevented. As a result, even in the case of multi-layer gold tri, which has a structure in which a Ti layer with a solder-diffusion prevention effect is inserted between a solder-wettable Cu layer, the solder diffuses through these pinholes and penetrates through several melts. It becomes one. Therefore, in the present invention, a multilayer metal layer is formed using AJ as a mask material, which has no pinholes even when deposited at a low temperature, or a multilayer metal layer formed by plating is used. FIG. 4 shows the number of melting times of the solder and the solder penetration rate at the pinhole portion. From this, it can be seen that compared to the conventional manufacturing method using Ti as a mask material, the multilayer metal layer manufactured by the manufacturing method of the present invention is superior in that there is no solder penetration.

Furthermore, with the manufacturing method using plating, it is possible to form a multilayer metal layer with excellent adhesive strength, and in addition, the number of mask alignments in the entire process up to the formation of solder bumps can be reduced compared to the conventional method or the method of the present invention. The patterning accuracy can be improved by reducing the number of times from three in the first embodiment to two.
Very fine terminals can be obtained.

Effects of the Invention As described above, according to the present invention, a multilayer metal layer without pinholes can be formed, penetration by molten solder can be prevented, and a connector having a structure in which solder bumps are stacked can be manufactured.

[Brief explanation of the drawing]

Figures 1 (a) to (υ) show the manufacturing process of the first embodiment of the present invention. @ Figure 2 (a) to (j) show the manufacturing process of the second embodiment of the present invention. Figure 3 shows a diagram illustrating the drawbacks of the board-to-board connector proposed by the applicant. Figure 4 shows the multilayer metal layer produced by the manufacturing method of the present invention and the multilayer metal layer produced by the conventional manufacturing method (Figure 6). The characteristics of the solder penetration rate and the number of times of melting with respect to the layer are shown in comparison. Figure 5 shows the configuration of the prior art inter-board connector proposed by the applicant. Figures 6 (a) to (h) ) shows the manufacturing method of the inter-substrate connector shown in FIG. 5.0 FIG. 7 shows a cross-sectional view of a multilayer gold IG layer (= solder bump formed) made using a Ti mask of the prior art. In the figure, n: polyimide film (12.5-25 μm) a
: Al1 1' : Cu m : T, i l: Cu 1': Cu O* O', O', 0ttt : Film resist section (N figure

Claims (3)

[Claims] (1) A first metal layer made of a first metal that is wettable with solder and a first metal layer that is not wettable with solder and that does not alloy with solder, on the first main surface of a supporting substrate that has insulating properties. A second metal layer made of a second metal, a third metal layer made of a first metal, and a fourth metal layer made of a fourth metal are laminated in order, and a second metal layer made of a second metal is layered on the second main surface. a step of forming a fifth metal layer, applying a resist on the fourth metal layer,
a step of etching the fourth metal layer using the mask after pattern formation to form a metal mask; a step of etching the first, second, and third metal layers using the metal mask; A resist is applied to the fifth metal layer placed on the surface to form a pattern and then used as a mask.
forming an opening in the fifth metal layer on the back surface of the remaining portions of the second, third, and fourth metal layers, the area of which is smaller than the remaining portion; and removing the support substrate from the opening of the fifth metal layer. etching to form a through hole reaching the first metal layer;
A step of forming a resist remaining pattern with an area slightly larger than the metal layer opening, a step of etching the fifth metal layer using the resist pattern as a mask, a step of etching away the fourth metal layer, and a step of removing the resist. step, placing minute solder balls through a mask directly above the first, second and third metal remaining portions on the first main surface;
In the manufacturing process of heating and melting, cooling and fixing to form a basic structure to which solder bumps are fixed, the fourth metal layer can be formed at 150 degrees Celsius or less, has no pinholes, and has a first metal layer. A method for producing an inter-board connector characterized by using a metal that does not dissolve in a chemical etching solution for the layer. (2) A method for manufacturing an inter-substrate connector in which an Al mask material is used as the fourth metal layer in the manufacturing method according to claim 1. (3) A first metal layer made of a first metal that is wettable with solder on the first main surface of the support substrate that has insulating properties, and a first metal layer that has wettability with solder on the second main surface. A step of forming a second metal layer made of a second metal, applying a resist to the second metal layer disposed on the second main surface to form a pattern and using it as a mask to form an opening in the second metal layer. a step of etching the supporting substrate from this opening to form a through hole reaching the first metal layer;
forming a third metal layer by selectively depositing on the metal layer a third metal that has no wettability with the solder and does not alloy with the solder; forming a fourth metal layer made of a fourth metal wettable with solder on the third metal layer by electrolytic plating, an area slightly larger than the opening of the second metal layer; forming a resist opening pattern on the first metal layer and the second metal layer, and using the resist pattern as a mask, forming a solder layer on the first metal layer and the fourth metal layer by electrolytic plating. A method for producing an inter-board connector, comprising: a step of forming a resist, a step of removing a resist, and a manufacturing step of heating and melting and cooling to form a basic structure to which solder bumps are fixed.