JPS62293664A - Protection circuit for MOS type integrated circuit - Google Patents

Abstract

PURPOSE:To improve an electrostatic withstanding voltage characteristic, in an input protecting circuit using poly Si for an input resistor, by forming a protecting semiconductor region having a conductivity type opposite to that of a substrate in front of the input resistor. CONSTITUTION:Protecting diodes D1 and D2 are formed with an impurity diffused region 8 and a substrate. The diodes are connected to an Al wiring layer through an input resistor 3, which is formed with polysilicon. Meanwhile, an n-type impurity layer 6 is formed in said substrate part. A part of the layer 6 is connected to the Al wiring layer 2 by using an n<+> layer 7. A junction part between the impurity layer 6 and the substrate part forms a second diode D4. In this constitution, static electricity inputted from the outside can be blocked by two stages of the diode D4 and the diodes D1 and D2. Dielectric breakdown 12 of a field oxide film INS, which is formed directly beneath the input resistor 3, can be prevented.

Description

[Detailed Description of the Invention] Five Detailed Descriptions of the Invention [Summary] In an input protection circuit using Si as an input resistor,
A protective semiconductor region of the opposite conductivity type to the substrate is formed in front of the input resistor to prevent high electrostatic voltage.

[Industrial application field]

The present invention relates to MOS type integrated circuits, and more particularly to improvements in input protection circuits for preventing internal elements from being destroyed when high static electricity is applied to the input terminals of the MOS integrated circuits.

[Conventional technology]

MOS-IOC) The resistance of the input bin is 1 due to the MOS structure.
Although it has a high resistance of 012 to 1o' [:Ω], it is weak against static electricity.

Therefore, a protection circuit is usually provided at the input section.

An example of a conventional protection circuit is shown in FIG. In FIG. 5, a poly(ν) S resistor 52 as an input resistor is connected to the test line 51 from the input bat, and a diode is connected between the terminal behind it and the high power supply Vca and the low power supply Vsa. D1. and D2'g are inserted and connected in opposite directions. And 2) input resistance R and diode D1. D2 disperses static electricity applied to the input bin.

Various protection circuits of this type have been proposed, but basically all of them are designed to disperse static electricity using an input resistor and a PN junction diode to prevent damage to the MOS circuit in the internal circuit.

FIG. 4 shows cross-sectional configurations of various examples of these conventional circuits.

Figure 4 (A) shows the most common configuration, with input B wiring 43 connected to the input pin and A2 wiring 4 connected to the internal circuit.
3', a low concentration n-base diffused resistance is interposed therebetween. In the figure, 41 is a low concentration p-type semiconductor substrate, INS is S
i It is an oxide film. The equivalent circuit of this protection circuit is shown in Figure 4CB.
), as shown in the figure, it is a composite circuit of a p-n junction diode D arranged in the opposite direction between the diffused resistance layer 42 and the substrate potential (ground), and the high voltage of static electricity is generated by the diffused resistor R. and are distributed by diode D to protect the internal circuit. However, in this case, when high static electricity is applied, as indicated by 44 in FIG.
If the AJL penetration reaches the PM board, the input terminals will be short-circuited, resulting in an input leak failure.

Therefore, an improved version of this is shown in FIG. 4(C), in which parts corresponding to those in FIG. 4(A) are designated by the same reference numerals. Here, in order to prevent the resistor from directly contacting the diffused resistance layer 42, a poly 5S45 (which also serves as an input resistor) is interposed. In addition, this is an attempt to completely solve the problem of input leak failure due to the penetration of the contact shown in Figure (A), but due to the high resistance of polyS, it generates heat during normal IC use, and the 5i0246 of the interlayer insulating film ,
Due to the poor heat conduction of 46', its dissipation is poor, and polyS
(There is a problem that the wiring and contacts may become damaged due to deterioration.

Fig. 4 (CD) shows an example in which a sandy soil thermal &6 layer 47 is used in place of poly S (poly S) in order to further solve the problem of poly f; io heat generation. layer 4
Introducing the process of forming 7 into the input circuit is troublesome in the IC manufacturing process,
2. Alternatively, it is desirable to solve the problem with polyS4.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional MQSIC input protection circuit,
There is a problem that input leakage failure occurs due to electrostatic breakdown of the AL electrode contact, and all conventional configurations that attempt to solve this problem have been insufficient.

Therefore, the present invention has developed an MQ that completely strengthens the protection of internal circuits, solves the problem of electrostatic damage, and is easy to process.
It is intended to provide a protection circuit configuration for SIC.

[Means for solving problems]

The present invention relates to a protection diode circuit for an integrated circuit formed on a semiconductor substrate of one conductivity temperature and using a Si layer as an input resistor, in which the input pin side of the input resistor is formed on the semiconductor substrate. Further, the impurity region of the opposite conductivity type extends below the connection portion between the input pin side aluminum wiring layer and the input resistor board IJS4 layer. The present invention provides a protection circuit for a MOS type integrated circuit characterized by the following features.

[Effect]

Taking the cross-sectional view of the device in FIG. 2(A) of the embodiment of the present invention, the B wiring layer is 2) Bo +) Ss wiring layer is 5, the connecting portion between the two is 5, and the above board is and a diffused region of opposite conductivity type. Therefore, application of high electrostatic voltage, voltage
) Due to the heat generation of Si, for example, the insulating film I is designated as 12.
Even if the NS is destroyed, since there is a diffusion region of the opposite conductivity type below it, input leakage defects can be prevented.

In addition, since the input A2 wiring is in contact with this diffusion region of the opposite conductivity type (the area is equal to the junction area of the rear protection diode), it is necessary to provide a protection diode before the conventional protection circuit due to the same constraints. , and the retention effect against static electricity is strengthened.

〔Example〕

FIG. 1(A) shows a plan configuration diagram of an embodiment of the present invention, and FIG. 2(, 4) shows an enlarged view of its cross-sectional configuration.

In FIG. 1 or 2, a low concentration p-type substrate SUB
Particularly, referring to FIG. 1(A), 1 is a pad connected to an input bin, 2 is a layer from the pad to (2) Aλ wiring layer, 3 is a silicon wiring layer (I) Si wiring layer, 4 is J
5ffi diffusion region (f!-w) formed in wiring layer and substrate
#JJ) Contact part with 6 (window part, 5 is Bo IJ)
, S<wiring layer 3 and AJ! This is a contact portion with the wiring layer 2. Further referring to FIG. 2(A), the contact portion 5 between the polyS (wiring layer 3 and the Aλ wiring layer 2) is formed using a thick insulating film IN.
A 60% impurity diffusion layer (depth 1-6μ cap size is 30
X 250 tsg&2. Carrier concentration 10','/
cm-') is provided. A layer 7 of a high concentration region for contact is provided in the impurity diffusion layer B, and the layer 7 is provided with an input AJ! The wiring layer is a contact (
Contact part 4). The above is a typical part of the present invention, and a normal O protection circuit is provided at a subsequent stage. In this embodiment, the % type impurity diffusion region 8 (depth 0
．． 3μ chicken, size 30 x 30μm2゜carrier concentration 10e761%-3) and low concentration outer mold diffusion region Cn
-waLg) 9 (depth 1~6 am + size is 70x70μm2. carrier concentration 10ξn ctr% -5
) is formed.

In addition, in this example, this low concentration? S-type diffusion region (?L-
vmLL) 9 is formed in a cross section different from that in Figure (A).
B). % temperature impurity diffusion region 8 has a void IJS (8 wired to the internal circuit via layer 31).
The wiring layer 2' is in contact. Further, the low concentration external type diffusion region (n-wtrlL) 9 is connected to the high power supply VaC in the n middle layer 11, and the pm impurity diffusion region 10
is formed and is in contact with the film wiring layer 2'.

FIG. 3 shows the input protection circuit of this embodiment constructed in this way. R corresponds to the resistance due to the poly-Si layer 3, the diode D4 corresponds to the pf & junction diode between %-wal16 and the substrate Ar-8, and Dl is 9
It corresponds to a p% junction diode with a 0%-wall and one layer of 10, and D2 corresponds to a p-circuit diode with one layer of 8 and a p-substrate.

In the embodiment, the input AJ wiring layer 2 and the lower power supply 'l1
A diode D4t was connected in the opposite direction between ss and ss, and a diode D4t was placed next to release the input negative static electricity to the 0Vaa side of the board. However, as shown by the dotted line in Figure 3, a diode D3 was added to dissipate the positive static electricity. It may be arranged to escape to the higher power supply Vce side.

Furthermore, in the embodiment, an example was shown in which a low concentration % type impurity diffusion region 6 was formed under the contact portion 5 between the B (I) Si wiring layer 3 and the B wiring layer 2; ), the external impurity diffusion layer 6' may be formed directly on the p-substrate to form the input diode D4't-.

Furthermore, in FIG. 2, the A2 wiring layer 2' to the internal circuit is brought into contact with the n+ layer 8 and the p middle layer 10, but the polyS layer 3 is extended and the n+ layer 8 and p
It may also be brought into contact with the middle layer 10.

Furthermore, a hole (I)Ss may also be interposed in the contact portion 4 between the Aλ wiring layer 2 and the n-middle layer 7 or 6'.

〔Effect of the invention〕

As described above, according to the present invention, since a protection diode is also provided in front of the input resistor, static electricity can be dissipated at the front stage, and transmission of high voltage to the internal circuit can be prevented by dividing it into two parts. This further strengthens static voltage countermeasures. In addition, by providing a well Cwall 6 ) t'' of a conductivity type opposite to that of the substrate below the input A2 wiring N2 and the poly S (connection portion 5 with the wiring layer), it is possible to prevent input leak failure when electrostatic damage occurs.

[Brief explanation of the drawing]

FIG. 1(,4), CE) is a planar configuration diagram of an embodiment of the present invention, FIG. 2(A), U? ) is a cross-sectional configuration diagram of an embodiment of the present invention, FIG. 3 is an equivalent circuit diagram of an embodiment of the present invention, and FIGS.
(D) is a block diagram of a conventional input protection circuit, and FIG. 5 is an equivalent circuit diagram of another conventional input protection circuit. 1: Pad, 2: A2 wiring layer, 3: Poly 8i layer, 4.5: Contact part, 6: % type impurity diffusion layer, 7: ♂" layer, 8: T & type impurity diffusion region, 9: Low concentration % Dredging diffusion area, 10:2 impurity diffusion area

Claims (2)

[Claims] (1) In a protection diode circuit for an integrated circuit formed on a semiconductor substrate of one conductivity type and using a poly-Si layer as an input resistor, an impurity of the opposite conductivity type formed on the semiconductor substrate on the input pin side of the input resistor. A protection circuit for a MOS type integrated circuit characterized by being connected to a region. (2) In the protection circuit for a MOS integrated circuit according to claim 1, the impurity region of the opposite conductivity type is placed under a connection portion between an aluminum wiring layer on the input pin side and a poly-Si layer of the input resistor. A protection circuit for a MOS type integrated circuit, characterized in that the circuit extends to the side.