JPS62293284A - Display unit with half-tone display function - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 5. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a character generator type display device, and in particular, to a high-definition display device, in order to emphasize displayed characters, an arbitrary Shading in which patterns of 2 and 3 are superimposed and displayed is suitable for displaying, and relates to a display device with a display function.

[Conventional technology]

In recent years, information processing devices such as personal computers and word processors are becoming more sophisticated and functional.

In such information processing devices, it is necessary to add special functions while maintaining a low price. For example, in order to emphasize the displayed characters, the display function for displaying shading by overlapping arbitrary patterns is not provided with special software, but instead places a heavy burden on the software, in order to avoid increased costs. The most common method was to use a bitmap method. However, the bitmap method has the disadvantage of slow processing speed.
A character synthesis method based on a Generator (hereinafter abbreviated as CG) has also been proposed. For example, JP-A-58-
The character generator control method described in Japanese Patent No. 169179 is one such method.

Hereinafter, a conventional technique of a character synthesizing device using the above-mentioned character generator control method will be explained with reference to FIGS. 12 and 13.

FIG. 12 is a block diagram of a personal computer display system circuit according to the prior art, in which 1 is a central processing unit (hereinafter abbreviated as MPU), 2 is an address bus, and 6 is a block diagram of a personal computer display system circuit according to the prior art.
is a data bus, 4 is a read/write signal line (hereinafter abbreviated as VN line), 5 is an address decoder that decodes the address of the circuit required for display, 6 is an address selection line, and 7 generates various timing signals for display. Cathode ray tube control circuit (
Cathodel (ay Tube Control
(hereinafter abbreviated as CRTC), 8 is a display address bus, 9 is an address line indicating the line position within each character (hereinafter abbreviated as raster address line), 10 is a display timing signal line indicating the display period, 11 is a cathode ray tube
a synchronizing signal line to the e-Ray Tube (hereinafter abbreviated as CRT), 12 an image generator, 15 a character clock signal line with a character unit period, 17 a first character code memory for storing character code information for display, 18 is an arbitrary pattern used for halftone display. The shaded area is a second character code memory that stores pattern code information, and these memories 17 and 18 are collectively referred to as display memory. 15 is a composite address bus that provides address information to the display memory, and 16 is a multiplexer that switches information sent to the composite R/WM 15 indicating read/write operations to the display memory by a signal provided on the display timing line 10. 19. 20 is a 6-state gate, each containing the first, character code memory 17,
The signal from the second character code memory 18 is controlled by the signal G1 on the first gate open signal line 3o and the signal G2 on the second gate open signal line 61 output from the gate signal generator 29.

21 is character pattern information (arbitrary shading is pattern information, 6
.

22.25 is a CG that stores C (j21
The signal (j5, second latch signal line 63) on the first latch signal line 62 output from the gate signal generator 29
It is controlled by the upper signal q4. 24 is the first latch 2
2. 1 circuit for ORing the output of the second latch 25, 25 is a parallel-to-serial conversion circuit, 26 is a display timing signal fls10
and a display timing generation unit that generates a display control signal from the information on the character signal line 13; 27 is a display control signal line;
8 is a CRT. Next, the operation of the above-mentioned prior art will be explained.

First, the updating operation of display contents will be explained.

In FIG. 12, the display content update operation is performed when the display timing signal line 10 is at a low level (hereinafter abbreviated as IL').
That is, it is performed during the non-display period. At this time, MPU1
becomes accessible to the first character code memory 17 and the second character code memory 1B, and the multiplexer 14 transfers the information on the address bus 2 to the composite address bus 15, l't/
The information on the W line 4 is sent to the composite R/W line 16. Therefore, MPUI has a character code of 4.

Information and shading can be updated to update pattern code information.

Next, the display operation will be explained. The display operation is performed when the display timing signal line 10 is at a high level (hereinafter abbreviated as 'H'), that is, during the display period.

That is, the multiplexer 14 sends the information on the display address bus 8 to the composite address bus 15, and
6 is fixed to the read operation. According to the information on the display address bus 8, information is read out from the first character code memory 17 and the second character code memory 18 at regular intervals. Here, the information stored in the first character code memory 17 is the address of CG21, that is, the character code of the character to be displayed, and the information stored in the second character code memory is the same address of CG21, but the shaded area indicates the pattern. It is a character code. However, when no pattern is added to the shaded area, the character code of the non-displayed character is stored in the second character code memory 18.

FIG. 13 shows signals G1. G2, Q3+
(This is a timing chart showing the relationship between the load signal of J4 and the display control signal line 27, and the timing of display operation will be explained below with reference to this diagram. Reading from the display memory is permitted, and the 6-state gate 19 is manually operated. When the signal G1 becomes 'H', the character code information from the first character code memory 17 is manually input to C(j21.
Since the reading is performed line by line, the character code information described above is combined with the information in the raster address block 9 to determine which character and line pattern information is to be read out. Next, the signal G5 input to the first latch 22 becomes 111', and the pattern information from C(j21 is held in the first latch 22. Furthermore, the signal G input to the second latch 23 becomes 111'.
4 becomes 1H', and the above pattern information changes 01 to circuit 2.
4 and is held in the second latch 26. At this time, the pattern information is also input to the parallel-to-serial conversion circuit 25, but since the signal on the display control signal line 27 is 1LI, it is not loaded into the parallel-to-serial conversion circuit 25. Next 6 state gate 2
When the signal q2 input to 0 becomes #H#, C(321
The character code information of the pattern is sent from the second character code memory 18 to the second character code memory 18, and the pattern information is determined by combining it with the information of the raster address H9. Furthermore, the first latch 22
The signal q6 input to the latch becomes 1H', and the pattern information is held in the first latch 22. The pattern information held in the first latch 22 is zeroed out from the information held in the second latch 23 by the OR circuit 24 and sent to the parallel-to-serial conversion circuit 25. At this time, the load signal on the display control signal line 27 is lH.
', the pattern information is loaded into the parallel-to-serial conversion circuit 25 and converted into serial video information.

By repeating the above operation several times for the character pattern lines to be displayed, one character that has not been synthesized can be displayed on the CRT 28.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the CG 21 reads the information in the display memories 17 and 18 once each during one character clock, for a total of two times.
Must be read twice. Therefore, in a high-definition display device with a fast character clock, there is a problem that the reading speed of a normally used display memory is not sufficient.

, 7.

For example, using Hitachi CRT: C14-219OA as a display device, the horizontal period is 665 μs, and the horizontal display period is 6968 μs.
s, in order to display 80 characters (640 dots horizontally), CRr is sent from the display control device once every 496 ns.
It is necessary to send serial data. At this time, for example, if NEC back μP41416C-12 (R/W cycle time 3Dons) is used as the display memory, the CG is
Since it is only necessary to read the information in the display memory once during s, it is possible to read the information sufficiently. However, in the conventional example described above, C(j
The information in the display memory must be read twice in 496 ns, which is impossible. In order to solve this problem, IIAM with a high readout speed may be used, but such RAM is generally expensive and leads to an increase in the cost of the display device, so this is not a fundamental solution.

Further, in the conventional example described above, the hatching pattern is limited to the pattern existing in CG. For example, as shown in FIG. 4(a), which will be described later.
A pattern like this is similar to a general cGl model made by NEC.
PD24256AC/D-Xol (JIsc6226te, 8.

It does not exist in the 453 specified non-kanji characters and 2965 first-level kanji characters). In order to use such a pattern as a hatching pattern, it is necessary to produce and use a CG that includes the pattern, which poses a problem of increasing the cost of the display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive display device with a shaded display function that can also handle high-definition display.

[Means for solving problems]

The above purpose is to use a CG display device that uses a character code memory and a character attribute memory as display memories, and is controlled by the information in the character attribute memory, and uses the raster address generated from cit'rc to create an arbitrary image for each raster. Shading, which combines a pattern with a character code pattern generated from CG, is achieved by providing a pattern combining section.

[Effect]

The shaded area indicates that the pattern synthesis unit generates an arbitrary pattern by encoding the same raster address at the same time that the CG sends out a pattern for each raster of the character code based on the raster address from the CRTC, and creates an arbitrary pattern for the characters sent out from the CG. Combine each raster of the pattern with the pattern. This composition is controlled by information in the character attribute memory.

As a result, the number of times the CG reads the display memory during one character clock is only one, and the shaded pattern does not need to exist in C(j).

〔Example〕

Hereinafter, embodiments of a display device with a shaded display function according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a personal computer display circuit showing a first embodiment of the present invention.

In FIG. 1, circuit blocks and signal lines having the same functions as those in FIG. 12 are given the same reference numerals.

34 is a character attribute memory that stores character attribute information;
This corresponds to the second character code memory 18 in FIG. The display memory is composed of the character attribute memory 64 and the character code memory 17. 55 is 16 dots x 16
Although this is a CG that stores dot character pattern information, arbitrary hatching that is combined with the displayed character pattern, such as C (321) in FIG. 12, does not need to include a pattern. The shaded lines from 37 to 37 indicate the raster address 2° signal line, and 68 indicates the raster address 2I signal line.
Signal line 69 is character pattern information CO~C from CG55
7 (described later with reference to FIG. 4), character pattern signal 40 outputs information on character pattern signal line 59 using information RAO on test address 2° signal line 67 and information RA1 on raster address 21 signal line 38. The shaded areas in CO to C7 are pattern synthesis units that add pattern information, and the control thereof is performed by the information NS on the signal line 56. The shaded line 41 is a composite pattern signal line for outputting composite pattern information MO to M7 from the pattern composition section 40.

Note that the display content updating operation of this embodiment follows the operation of the conventional example described above, except for one point below. That is, whereas the second code memory 18 in the conventional example shown in FIG. 12 stores pattern code information in the shaded areas, in the embodiment shown in FIG. This is the point where information is stored.

Next, the display operation of this embodiment will be explained.

, 11.

The display operation is performed when the information on the display timing signal line 10 is In2.
, that is, during the display period. That is, when the multiplexer 14 sends out the display address bus 8 to the composite address bus 15 and fixes the composite R/W line 16 to the read operation. According to the address output to the display address bus 8, information is read out from the character code memory 17 and the character attribute memory 34 at regular intervals. At this time, the raster address information from the raster address Shinseigan 9 is added to the character code information read from the character code memory 17 to determine the address of the CG 35. Cti35 is 1
C of 6 dots x 16 dots (because it is j, divide the 16 dot pattern for the - character raster into two, and use the first character clock to divide 8 dots on the left, and the next character clock to divide 8 dots on the right. The information CO to C7 on the character pattern signal lines 6 and 9 is output to the character pattern signal line 39.
When the information NS of M66 is In2, that is, when executing the shading, pattern information is added to the shading by using RAD and rib 1, and then outputted to the composite pattern signal 12 line 41. Further, when NS is L, that is, when display is not performed on the shaded lines, CO to C7 are outputted to the composite pattern signal line 41 by the pattern synthesis section 40 without adding any pattern information. Information MO to M7 of the composite pattern signal line 41 is input to the parallel-to-serial conversion circuit 25,
It is loaded by a signal on the display timing signal line 27 outputted from the display timing generation section 26, parallel-serial converted, and then outputted to the CRT 2B. The CRT 28 transfers information from the parallel-to-serial conversion circuit 25 to the synchronization signal line 1 from the CRTC.
The images are displayed in synchronization with the synchronization signal No. 1. The above is an overview of the operation of this embodiment.

Next, the shaded areas explain and explain the patterns. If the shading is only displayed discontinuously on the screen and discontinuously with the displayed characters, the pattern of the shading may be any pattern as long as the displayed characters can be recognized. but,
When the shading is displayed on the entire text, that is, when the shading is displayed continuously vertically, horizontally, and diagonally, the pattern of the shading is not interrupted between letters (it is easier to see if it is continuous). In order to do this, it is necessary to make the shading pattern a combination of an integer number of basic patterns in the vertical and horizontal directions.Also, in this embodiment, a 16 dot x 16 dot C pattern is used.
(Since 335 is used, the 16 dot information for one character raster is manually entered into the pattern synthesis section for 8 dots on the left and right for the shading, but the shading is created using the raster address of the present invention. Due to this nature, it is safe to assume that the pattern of shading every 8 dots on the left and right is the same.

FIG. 2 is a diagram showing an example of execution of synthesis according to the present embodiment shown in FIG. 1, and FIG. 2(a) is used for this embodiment. The shaded area that satisfies the above two conditions is the pattern diagram, the second
FIG. 2(b) is a display character pattern, and FIG. 2(C) is a combination of the shaded pattern in FIG. 2(a) and the display character pattern in FIG. 2(b). Figure 2(d) shows 4 dots
This is a basic pattern of four dots, and FIG. 2(a) shows this pattern repeated four times in the vertical and horizontal directions.

In FIG. 3, the shaded area in FIG. 2(a) is a table showing the relationship between patterns and raster addresses. FIG. 5(a) shows - character raster patterns Po to P7 and raster addresses RAO to R, A3.
This is a table showing the relationship between FIG. 5(a) is a table showing the relationship between - character raster patterns PO to P7 and raster addresses RA[l to RA3. As you can see from this table, PO~
The even numbered bits of P7 are always 'L', that is, no information is added to the displayed character pattern information.Furthermore, when the raster address is an odd number, the next bits of PO to P7 are always 'L'.

This shaded area indicates that the basic pattern is a 4 dot x 4 dot pattern, so the relationship between the lower two bits of the raster address (RA1, RAD) and the odd bits of the pattern is as shown in Figure 6 (0)). . In other words, elbow 0
== When 'H', P7 to P1 are all 'L', 臥1=
When RAO = 'L' in 1LI, Pl and P6 are 'H',
When RA1 is 'H' and FtAO = 'L', P5 and P
l becomes 'HI.

Hereinafter, the shaded pattern synthesis section 40 for synthesizing patterns will be described.

In FIG. 4, the shaded area is a circuit diagram of the pattern synthesis section 4o,
Circuits and signal lines having the same functions as those in FIG. 1 are given the same reference numerals.

, 15.

In the figure, the pattern synthesis section 40 (shaded) is composed of three parts: a basic signal generation section 51 , a control section 52 (shaded), and a pattern synthesis section 55 .

The basic signal generating section 51 is composed of a NOTOR gate 49, an OR gate 46, and an AND gate 44.
, RAO generates the basic signals necessary for pattern synthesis. That is, RAO with RAl = 'L'
= "N when 'L'('H' is output from JR gate 43, AN when RA1 = 'H' and RAD = 'L'
1H' is output from the D gate 44.

The shaded areas indicate that the control unit 52 uses the information on the shaded signal line 36 to
Controls the execution of shading. Shading is information NS of signal line 66
When is 'L', that is, when the shaded area is not displayed, A
The NDNO gate 46 always sends the IL' output to the pattern synthesis section 55 regardless of the input from the NOR gate 45 and the peak gate 44, respectively.

The pattern synthesis section 53 connects the character pattern signal line 39 (CO
The shaded portions serve to add pattern information to the information of ~C7) and pass it to the composite pattern signal line (Mo~M7). That is, the OR gate 50.48 performs an OR with the output of the gate 45 and the information of C7, C5, and 16°, respectively, and obtains Ml,
output to M3, and OR gates 49 and 47 output C5 and CI, respectively.
ORQ the information of and the output of the ANDNO gate to M5.
, output to Ml. Information on C6, C4, C2, and CD is
Just M6. M4. M2. Passed to MO. The above is the operation of the pattern synthesis section 40 shown in shaded areas.

In the present invention, CG35 during one character clock
is character code memory 17 out of display memory 17.34
It is enough to read only once. Therefore, in the present invention, a RAM with a slow R/W cycle time can be used as the display memory even in high-definition display, but such a RAM has a lower R/W cycle time than the display memory used in the conventional high-definition display described above.
It is cheaper than AM.

Furthermore, in the present invention, the creation of the hatched butter y is performed only using raster address information. Therefore, any shaded pattern does not need to be included in C(j).

As a result, the present invention is inexpensive and can compose an arbitrary shaded pattern regardless of the character pattern existing in C(j), and constitutes a display device with a shaded display function that can also handle high-definition display. Can be done.

Also, in the present invention, a plurality of different shading patterns can be generated. A second embodiment of the present invention in which three kinds of shading patterns can be used is shown in FIGS. 5, 6, and 7 below.
This will be explained using figures.

FIG. 5 is a block diagram of a personal computer display system circuit showing a second embodiment of the present invention in which three types of shaded patterns can be selected and used, and includes circuit blocks having the same functions as those in FIG. Signal components are given the same reference numerals.

In the figure, the shaded area 54 is a pattern selection and synthesis section, and the shaded area in FIG. 1 corresponds to the pattern synthesis section 65. 55
The shaded line indicates the selection 2° signal line, the shaded line 56 indicates the selection 21 signal line, and 57 indicates the task address 22 signal line.

The update and display operations of the embodiment shown in FIG. 5 are as follows: The shaded areas in FIG. The shaded area generates a pattern, and the shaded area indicates the signal line 6.
6 was controlled by the information NS, whereas the 5th information NS
Shading in the figure indicates pattern selection synthesis 54G-FMO and 1 (AI).
and the information RA2 on the task address 22 signal line 57 generates a pattern, and the selection is controlled by the information NSO on the selection 2 signal line 55 and the information NS1 on the selection 21 signal M56. According to the first embodiment of the present invention shown in FIG.

Next, the three types of hatching patterns in the second embodiment will be explained.

FIG. 8 is a diagram showing an example of implementation of the second embodiment of the present invention.
This is the non-display pattern at the time of , that is, no shading is performed. In Fig. 8 (0), the right diagonal shading is the pattern when Y (1) = N81・NSO, and in Fig. 8 (c), Y (2) =
The loose tether pattern for NS1-NSO is shown in Figure 8 (d
) is a pattern when Y (5) = NS1·Neo. The pattern for dense shading is the same as the pattern for shading based on the basic pattern of 4 dots x 4 dots of the first embodiment of the present invention shown in FIG. 1, and the pattern for loose shading is based on this pattern. ='H' and RAO='
The pattern for H' is thinned out, and the right diagonal shading is a pattern obtained by thinning out the right diagonal continuous pattern every row.
Since it is a 9° item and the basic pattern is 8 dots x 8 dots,
Information on RA2 was needed. The operation of the shaded pattern selection and synthesis section 54 that generates the above patterns will be explained with reference to FIG.

In FIG. 7, the shaded area shows the circuit of the pattern selection and synthesis section 540, and elements and signal lines having the same functions as those in FIG. 4 are given the same reference numerals.

In the figure, the shaded circuits of the pattern selection and synthesis section 54 are the basic signal generation section 51, the decoder section 74, the bit synthesis control section 75, the raster synthesis control section 76, and the pattern synthesis section 53.
It is composed of 05 parts.

The decoder section 74 is a NOT game) 58.59.60.
<Sl and NAN D game) It is composed of 62, 63, 64, and input N81 and NSO as Y(o)
, Y,(1), Y(2).

The raster synthesis control section 76 is an AND gate, 72.75
The pattern is controlled for each raster. Y(0
) is selected, that is, when the output of the NAND gate 62 is 1L', the AN, D gates 72 and 75 output -L' bits, 20 regardless of the input from the basic signal generator 51.

It is sent to the synthesis control section 75. Therefore, when Y(0) is selected, no shading is displayed. When Y(2) is selected, the output of the AND gate 73 is always IL', and P
A pattern where A1='ll' and R, A O='H' is thinned out.

The bit synthesis control section 75 includes NOTOR gate 66R gates 66, 67, AND gates 6.8.69.70.71
, and when Y(1) is selected, by RA2,
The outputs of MO to M7 are controlled for each odd bit. In other words, when PA2-'L', the output of AND game) 69.7CJ is always IL regardless of the output of the raster synthesis control section 76.
', and when PA2='H', AND gate 7
The outputs of 58 and 71 are always K#L#. When Y(1) is not selected, the outputs of OR gates 66 and 67 are always ``H'', and the outputs of 68, 69, 70, and 71 depend only on the output of raster synthesis control section 76. .

Furthermore, when none of Y(0), Y(1), and Y(2) is selected, a densely shaded pattern is displayed. The above is the operation of the pattern selection and synthesis section 54 shown in shaded areas.

As described above, according to the second embodiment of the present invention, the user can select character attributes from among the patterns by using software, which is inexpensive and does not depend on character patterns existing in CG. By rewriting the contents of the memory, it is possible to configure a display device with a display function, which can be freely selected and synthesized, and which can also support high-resolution display.

The shading pattern used in this example can be easily extended to CG cover patterns in which the number of vertical and horizontal dots is a multiple of 8. Furthermore, the shading pattern used in this example does not disturb the pattern even between characters. This has the effect of making the overlaid characters easier to see and emphasized.

Additionally, the present invention allows user-defined shading patterns to be generated. A sixth embodiment of the present invention in which a user-defined shading pattern can be used is shown in FIG. 8 and 9 below.
This will be explained using FIG. 9, FIG. 10, and FIG. 11.

FIG. 8 is a block diagram of a personal computer display system circuit showing a third embodiment of the present invention in which a user-defined shaded pattern can be used, and the circuit has the same functions as those in FIGS. 1 and 5. Blocks and signals iK are labeled with regular symbols. In the figure, 77 is a shaded pattern synthesis section, 78 is an 8-bit register that stores a user-defined 8-bit pattern, 79 is an 8-bit register address selection signal gland, and 80 is a pattern information UDO~ from the 8-bit register 78. The shaded line 7 is a data signal line sent to the pattern synthesis section 77.

The updating and display operations of the embodiment shown in FIG. 8 are performed by the network composition unit 40 shown in FIG.
The shaded area generates a pattern, and the shaded area is controlled by the information NS on the signal line 36, whereas the shaded area in FIG. 7 is used to generate the shading pattern, except that the shading is selectively controlled by the information NSO on the selection 2 signal line 55 and the information NSI on the selection 21 signal line 56. According to the example given below.

Next, the shading pattern of the third embodiment of the present invention will be explained.

FIG. 9 is a diagram showing the shaded pattern of the third embodiment of the present invention. FIG. 9(a) is an example of an 8-bit pattern that can be set arbitrarily by the user. The reason why it is 8 bits is that a 16 dot x 16 dot CG character pattern is divided into left and right 8 bits and output. With this 8-bit pattern, display patterns for non-rope and three types of hatching can be generated, and the control is performed by N8 (1 and N81).

That is, when Y(o)=N S 1・NSO, it becomes a non-display pattern, when Y(1)=N 81・NSO, it becomes a vertical striped pattern shown in ) in FIG. 9, and Y(2)=
When N 81・NSO, the right diagonal pattern shown in FIG. 9(C) is obtained, and when Y(3)=N S 1・NSO, the left diagonal pattern shown in FIG. 9(d) is obtained. .

Next, the shaded area that generates the above pattern is the pattern synthesis section 7.
The operation of No. 7 will be explained.

In FIG. 10, the shaded area is the circuit diagram of the pattern synthesis section 770, and elements and signal lines having the same functions as those in FIGS. 4 and 7 are given the same reference numerals. The circuit includes a pattern generation section 81 and a pattern synthesis section 90.

The pattern synthesis section 90 is composed of OR gates 82, 83, 84, 85, 86, 87, 88, 89, and each synthesizes the signals of CO to C7 with each bit output of the pattern generation section 81, Output to MO~M7.

FIG. 11 is a circuit block diagram of the pattern generation section 81, and this pattern generation section 81 includes an 8-series (2→1) selector? The pattern shift section 95 consists of eight (4→1) selectors 98, and eight (2→1) selectors 93.

Next, the operation of the pattern shift section 95 will be explained.

The pattern shift unit 95 converts the information on the data signal line 80 into 8
Continuation (4 → 1) UDO to human power 0 and human power 2 of selector 98 ~
I) UD6. to input 1 in the order of D7. UD7. U.D.O.
~UD5 in order, manpower 3, UD2~UD7. UDO,
Manually select in the order of UDl, NSO' (l - upper, 1 (A1 as lower), 2 bits, UD' o ~ UD' 7
Output as . UD'O~UD' 7 is UDO~U
When D7 is N5O-RA1, 2 bits to the left, NSO・1
(When it is A1, it is shifted by 2 bits to the right.

Further, input UD' 0 to UD' 1 in the order of UD' 0 to UD' 7 to the manual input 0 of the 8-series (2→1) selector 93, select it by RA2, and output it as UD#0 to UD' 7. Ru.

These UD'O~UDI7 are UD' when RA1=1
0 to UD'7 are further shifted by 4 bits (a 4-bit shift of an 8-bit pattern has the same value on both the left and right sides).

The 8-series (2→1) selector 94 inputs the output of the pattern shift section 95 to input 1, inputs UDO to UD7 to the 8-series (2→1) selector 920, and manually inputs all 0s to 008 bits. , NSo is manually input to input 0, and N81 is used to select and output the output. The 8-series (2→1) selector 97 inputs this output to the human power 0, manually sets 0 to all 8 bits of the human power 1, and outputs the result selected by RAD to the pattern synthesis section 90. The above is the operation of the pattern synthesis section 77 shown in shaded areas.

As described above, according to the third embodiment of the present invention, it is possible to use a pattern for the shading defined by the user, regardless of the character pattern existing in CG, at low cost, and also for high-definition display. Compatible shaded areas can constitute a display device with a display function. Furthermore, if the character attribute memory is set to 8 bits or 16 bits per character like the character code memory, the fifth embodiment can also have the functions of the first and second embodiments.

〔Effect of the invention〕

As explained above, according to the present invention, in a display device with a display function, it is possible to synthesize any shading pattern regardless of the character pattern existing in CG, and also to synthesize a CG pattern in one character. (Since j reads the display memory only once, it is possible to use a memory with a slow R/W cycle time even in high-definition display. Such W is similar to the RAM used for conventional high-definition display. Since it is cheaper, shading is effective in reducing the cost of display devices with display functions.Also, it is possible to combine multiple shading patterns by allowing the user to select and synthesize multiple shading patterns by rewriting the character attribute memory using software in one circuit or user-defined. The shaded area allows for easy construction of a circuit for synthesizing patterns.

Furthermore, the character attribute memory can store multiple pieces of information 927° at the same time, such as character attributes other than the shading, such as inverted character display and blink character display, and the shading is displayed with a display function, which has an excellent function except for the drawbacks of the above-mentioned conventional technology. equipment can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a personal computer display system circuit showing a first embodiment of the present invention, the second diagram shows the relationship between the pattern and the raster address, and the shaded part in FIG. 4 shows the circuit of the pattern synthesis section. Figures 5 and 5 show three types of shaded patterns. Figure 7 shows a circuit diagram of the pattern selection and synthesis section, and Figure 8 shows the user's A defined shaded area is a block diagram of a personal computer display system circuit showing a third embodiment of the present invention in which a pattern can be used. Figure, 12th
The figure is a block diagram of a personal combinatorial display system circuit according to the prior art.
(J2. is a timing chart showing the relationship between <=4 and the load signal of the display control signal. 1...MPU, 5...Decoder, 7...CRTC
, 12... Oscillator, 14... Multiplexer, 17
...Character code memory, 25...Parallel-serial conversion circuit,
26...Display timing generation unit, 28...CRT,
34 ・=Character attribute memory, 65...C(j, 40・
...The shaded area is the pattern synthesis section, Figure 1, Figure 2, Maro ((1) (b> (C) (d) δ Ward (ku), 4th Senbunkoha 0 turn signal Maro (8 Hi" 7 To) 3? Go υ＼゛Koon Tai (8go, 71-) 8th qth flash (α) LoFgon nd] User 1 Banoon 7-'' 1st/flash L
, J No. 120

Claims (1)

[Claims] 1. A cathode ray tube that displays characters, figures, etc., a character code memory that stores character code information, a character attribute memory that stores character attribute information, and a character generator that generates character pattern data from the character code information. , a display device with a hatching display function, comprising a cathode ray tube control circuit that reads the character code memory and generates continuous addresses for displaying on the cathode ray tube and a raster address to be given to the character generator; A hatching pattern synthesis section is provided which is controlled by character attribute information read from the memory and synthesizes an arbitrary pattern for each raster with the character code data generated from the character generator based on the raster address generated by the cathode ray tube control circuit. . A display device with a shading display function, characterized in that it is configured to be able to synthesize any shading pattern regardless of the character patterns existing in the character generator.