JPS62290239A - Method for detecting synchronization/asynchronization area in looped communication system - Google Patents

Abstract

PURPOSE:To allow a simple hardware to detect the errors of critical values by permitting a control station to store two critical values in a border display area between synchronizing and asynchronizing areas and to transmit said values and providing each station with a comparison means comparing said two critical values. CONSTITUTION:In the packet exchanging part of each station, a border display area detection part 79 monitors a time slot number and detects the limit display area 21. Critical values between line switching area 25 and a packet switching area 27, both of which the control station transmits, are mounted in the area 21. The area 21 is composed of two time slots, and critical values are loaded in one time slot. The same critical values are simultaneously transmitted to two time slots. The contents of a 1st time slot are set to a critical value register 77, and a comparision part 81 compares them with the contents of a 2nd time slot and outputs the result to a packet switching area detection part 83. If the compared result has no error, the part 83 compares the contents in the register 77 with the time slot number and detects the area 27. If the compared result has errors, no detection is made with respect to the area 27.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Field of Industrial Application) The present invention relates to a synchronous/asynchronous area detection method for a loop communication system.

(Prior Art) Recently, network systems are being developed that interconnect a plurality of information systems (stations) via data transmission paths to realize more advanced information processing.

For example, process control networks and office
- Networks for automation (OA), networks for engineering automation (EA), networks for factory automation (FA), etc. have been developed.

There is a need for the development of large-scale, high-speed networks that can integrate or combine these independently existing networks to enable even more sophisticated information processing. The following requirements are required for such a large-scale network.

■ A high-speed, long-distance network.

■ It must be a multimedia network that can handle various media such as audio, still images, videos, and code data.

■ The network must be able to integrate circuit switching and packet switching.

■ The network must be capable of accommodating a wide variety of terminals and connecting various types of networks as branch lines.

As a network that meets the above requirements, a loop communication system has been adopted because of its compatibility with circuit switching systems, the ease of using optical communication technology, and the ability to configure a large-scale network system.

In such a loop communication system, a frame circulates within the loop at regular intervals, but it is possible to divide the frame into a circuit switching area and a packet switching area so that it can handle both circuit switching and packet switching. It is being done.

In order to optimize the number of terminals accommodated, their types, and the traffic level, and also to cope with instantaneous increases in traffic and the number of terminals, we changed the bandwidth in the circuit switching area and the packet switching area, that is, in the circuit switching area. It is necessary to dynamically change the area of the packet exchange area.

FIG. 5 is a diagram showing the configuration of such a loop communication system, in which control station 1 and each station 3,5,7,9 are connected to transmission line 1.
They are connected by 3.

Zarani station 3.9.11 has synchronous terminals 15a, 15b, 1
5G is connected, and the station 5.7.9 has an asynchronous terminal 17a,
17b and 17c are connected.

FIG. 6 shows the frame format used in this loop communication system, and the frame consists of a frame synchronization area 19, a boundary display area 21, a control area 23, a synchronous (circuit switching) area 25, and an asynchronous (packet switching) area. Area 2
7 and is generated by the control station.

Note that a frame is composed of a large number of time slots, and each area is a collection of several time slots.

The frame synchronization area 19 indicates the beginning of the frame, and the boundary display area 21 indicates the circuit switching area 25 and buckets 1 to 1.
The boundary values of the exchange area 27 are shown.

In the control area 23, the circuit switching area 2
Control data and the like for allocating the 5 time slots are communicated.

In the circuit switching area 25, communication between synchronous terminals is performed using the time slots assigned according to the above control data.

In the packet exchange area 27, each station detects the start of this area using the boundary value in the boundary display area 21 and performs packet exchange.

In such a system, the control station 1 centrally allocates time slots 1 to 1 for time slot exchange and requests/releases time slots from each station 3,5,7,9,11. When the control station 1 determines that the bandwidth of the circuit switching area 25 is low due to an increase in requests for time slots from each station,
Alternatively, if it is determined that the number of time slots released increases and the bandwidth of the circuit switching area 25 is left over, the bandwidth of the circuit switching area 25 and the packet switching amount 1fc27 is allocated.
It is dynamically changed according to the boundary value in the boundary display area 21. Therefore, if the boundary value is mistakenly detected at each station 3.5.7.9.11, a collision between circuit switching and packet switching may occur.

In order to avoid such a situation, error detection for boundary values is required. Error detection methods include parity check and CRC, but parity check cannot handle 2-bit errors, and CR
The C method has problems such as an increase in the amount of hardware.

(Problems to be Solved by the Invention) The synchronous/asynchronous area detection method of the conventional loop communication system has a problem in that it cannot detect errors due to its simple configuration.

The present invention was made in view of these problems, and its purpose is to provide a highly practical synchronous/asynchronous region detection method for a loop communication system that can configure boundary value error detection with simple hardware. It is about providing.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention connects a control station and a plurality of stations in a loop through a transmission path, and the control stations mutually change areas. A frame having a possible synchronous area for circuit switching, an asynchronous area for packet switching, and a boundary display area indicating the boundary between the synchronous area and the asynchronous area is circulated on the loop-shaped transmission path at regular intervals, and each station When communication is performed using the synchronous area and the asynchronous area, and the control station changes the area between the synchronous area and the asynchronous area, the control station sets the boundary value between the synchronous area and the asynchronous area in the boundary display area. In a synchronous/asynchronous area detection method for a loop communication system that circulates a changed frame, the control station stores two of the boundary values in the boundary display area and sends them out, and each station stores two of the boundary values in the boundary display area. The present invention has comparison means for comparing the two boundary values, and detects errors in the boundary values based on the comparison results.

(Operation) Therefore, the control station sends out two identical boundary values in the boundary display area, each station compares these two boundary values, and detects an error when it determines that the two boundary values are different. When it is determined that the two boundary values are the same, the area change process between the synchronous area and the asynchronous area is performed.

(Example) Embodiments of the present invention will be described in detail below based on the drawings.

The configuration diagram and frame format of the loop communication system in the following embodiments are the same as those shown in FIGS. 5 and 6, and the data in each time slot is m
81c encoded.

FIG. 3 is a block diagram showing the configuration of a station (for example, station 9), and station 9 includes a transmitter 29, a receiver 31, a loop interface 33, a frame controller 35, a transmission/reception controller 37,
It is composed of a PU 39, a memory 41, a synchronous terminal 43, and an asynchronous terminal 45.

The transmission/reception control section 37 includes a control section 47, a line switching section 49, and a packet switching section 51.

The control unit 47 performs packet communication of control data under the control of the CPtJ 39 using the control area 23 on the frame.

The control area 23 is detected when the CPU 39 registers the control area 23 in the register in the control unit during system configuration.
This is done by setting the start time slot number and end time slot number.

That is, it is detected by comparing the output of the slot counter with a register in which a start time slot number and an end time slot number are set. (This method is
The same applies to the line switching section and the packet switching section. ) The control unit 47 constantly monitors the inside of the control area 23, and if it detects a packet addressed to its own station, it receives it, and if there is transmission data, it detects empty data and transmits it. The transmitting station releases the used control area 23.

The circuit switching unit 49 performs transmission and reception using time slots 1 to 1 in the circuit switching area 25 specified by the CPtJ 39. The packet switching unit 51 performs packet switching communication using the packet switching area 27 on the frame. I do.

FIG. 4 is a block diagram showing the detailed configuration of the frame control section 35, and this frame control section 35 includes the serial/parallel conversion section 5
3. Latch section 55, descrambler section 57, word counter 59, word synchronization section 61, frame synchronization section 63, slot counter 65, scrambler section 67, C bit insertion section 69, frame transmission control section 71, selector section 73,
It consists of a parallel-to-serial converter 75.

The reception data and reception clock extracted by the receiver 29 are
The signal is input to the serial/parallel converter 53 via the loop interface 33 . The latch section 55 receives the output of the serial/parallel converter 53 as an input, and is latched by the output clock of the word counter 59. The output of the latch section 55 is output to the word synchronization section 61, the frame synchronization section 63, the selector section 73, and the descrambler section 57. Descrambler section 57
The output is given to the transmission/reception control section 37 as received data.

The word synchronization unit 61 and word counter 59 check the C bit to detect word synchronization. The word synchronization unit 61 constantly monitors the C bit, and determines that word synchronization has been lost when an error in the C bit is detected twice in succession. The error detection signal from the word synchronization section 61 is output to the word counter 59. When word counter 59 receives this signal, it shifts the clock to latch section 55 by one bit and outputs it. The word synchronization section 61 inputs the output signal of the latch section 55 which has been shifted by one bit, and checks C-pitch 1~. The above operations are repeated until word synchronization is established.

When the frame synchronization unit 63 detects the beginning of the frame, it initializes the slot force/kuntaro 5.

The slot counter 65 is initialized by the output of the frame synchronizer 63, and is counted up word by word by the output of the word counter 59. The output of the slot force "Kuntaro 5" is outputted as a slot number to the transmission/reception control unit 37 along with the word crotter and the received data.The transmission/reception control unit 37 divides the received data according to the slot number.

In response to a transmission request from the transmission/reception control section 37, the frame transmission control section 71 switches the selector section 73 from the output of the latch section 55 to the transmission data side that has passed through the scrambler section 67 and the C bit insertion section 69. The output of the selector section 73 is parallel-to-serial converted by a parallel-to-serial converter 75 and output to the transmitter 31 via the loop interface 33.

The transmitter 31 inputs the bit serial data from the parallel-to-serial converter 75, processes it using the reception clock, and outputs it.

FIG. 1 is a block diagram showing the detailed configuration of the packet exchange section 51, which includes a boundary value register 77, a boundary value display area detection section 79, a comparison section 81, a packet exchange area detection section 83, a receiver. 85, driver 87,
It consists of a media access control section 89.

The boundary display area detection unit 7 monitors the time slot number and detects the boundary display area 21. Boundary display area 21
The boundary values of the circuit switching area 25 and the packet switching area 27 that are transmitted by the control station are loaded.

FIG. 2 is a format diagram of this boundary display area 21. As shown in the figure, this boundary display area 21 consists of two time slots, a boundary value is loaded in one time slot, and the value of the same boundary value is Continuously transmitted to two time slots. The contents of the first time slot are the boundary value register 7.
7 and compares the contents of the next time slot with the comparison section 8.
Compare by 1. The result is output to the packet exchange area detection section 83.

Packet exchange area IL! If there is no error in the comparison result, the 1 detection unit 83 compares the contents of the boundary value register 77 with the time slot number and detects the packet exchange area 27.

Upon detection, receiver 85 and driver 87 are enabled. If there is an error in the comparison result, packet exchange area 2
7 is not detected.

The output of the receiver 85 and the input of the driver 87 are respectively connected to a packet-switched media access control section 89.

The final number of time slots in the packet exchange area 27 is set in advance by the CPU 39.

As described above, in this embodiment, two boundary values of the circuit switching area 25 and the packet switching area 27 are stored and transmitted in the frame boundary display area 21, and these two values are stored in the packet switching section 51 of each station. If the result of the comparison is correct, the packet exchange amount t@27 is detected, so it is possible to easily detect an error in the boundary value.

In this embodiment, the boundary chain length is one time slot length, but it goes without saying that it may be configured with a plurality of time slots.

[Effects of the Invention] As described above in detail, according to the present invention, the boundary between the synchronous area and the asynchronous area can be reliably detected in each station using simple hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a packet switching section of a station according to an embodiment of the present invention, FIG. 2 is a format diagram of a boundary display area in the same embodiment, and FIG. 3 is a block diagram of the configuration of a station in the same embodiment. , FIG. 4 is a block diagram of the configuration of the frame control section in the same embodiment, FIG. 5 is a schematic configuration diagram of the loop communication system, and FIG. 6 is a frame format diagram.

Claims (1)

[Claims] A control station and a plurality of stations are connected in a loop through a transmission path,
The control station transmits a frame having a synchronous area for circuit switching, an asynchronous area for packet switching, and a boundary display area indicating the boundary between the periodic area and the asynchronous area on the loop-shaped transmission path at regular intervals. each station communicates using the synchronous area and the asynchronous area, and when the control station changes the area between the synchronous area and the asynchronous area, the synchronous area and the asynchronous area of the boundary display area are changed. In a synchronous/asynchronous area detection method for a loop communication system that circulates a frame in which the boundary value with the area has been changed, the control station stores two of the boundary values in the boundary display area and sends them out, and each station A synchronous/asynchronous area detection method for a loop communication system, comprising a comparing means for comparing the two boundary values in the boundary display area, and detecting an error in the boundary value based on the comparison result.